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PRELIMINARY
March 8, 2000
SX52BD100
Configurable Communications Controller with EE/Flash Program Memory, In-System Programming Capability, and On-Chip Debug
1.0
1.1
PRODUCT OVERVIEW
Introduction
On-chip functions include two 16-bit timers with 8-bit prescalers supporting different operating modes (PWM, simultaneous PWM/capture, and external event counter), a general-purpose 8-bit timer with prescaler, an analog comparator, a brown-out detector, a watchdog timer, a power-save mode with multi-source wakeup capability, an internal R/C oscillator, user-selectable clock modes, and high-current outputs.
The Scenix SX52BD100 is a member of the SX family of configurable communications controllers fabricated in an advanced CMOS process technology. The advanced process, combined with a RISC-based architecture, allows high-speed computation, flexible I/O control, and efficient data manipulation. Throughput is enhanced by operating the device at 100 MHz and by optimizing the instruction set to include mostly single-cycle instructions. In addition, the SX architecture is deterministic and totally reprogramable. The unique combination of these characteristics enables the device to implement hard real-time functions as software modules (Virtual PeripheralTM) to replace traditional hardware functions.
SLEEP Clock
OSC1 OSC2 OSC Driver
C lock S elect
WDT Clock 8-bit Watchdog Timer (WDT)
RTCC 8-bit Timer RTCC Interrupt Stack 8 3 Port B COMPARATOR 4/8 8 8 8
4M H z Internal R C O SC (divided by 8 steps) System Clock
Power-On Reset Brown-Out
MCLR RESET MIWU 8 PC 8 Level Stack W System Clock
Prescaler for RTCC or Postscaler for WDT
Interrupt
MIWU 8
Port A Port C Port D Port E 8 8 8 8 8
Instruction 8 Pipeline Fetch
D ecode
Internal Data Bus 8 8 8 Address
8
8
FSR PC STATU S O PTIO N M ODE
ALU Data 262 Bytes SR A M
In-System D ebugging In-System Program m ing 4k W ords EEPR O M
Port B 16-Bit Timer 1 8-Bit Prescaler
Port C 16-Bit Timer 2 8-Bit Prescaler
Execute W rite Back
Address
12
8
W rite D ata R ead D ata 8 Instruction 12
IR EAD
Figure 1-1. Block Diagram
ScenixTM and the Scenix logo are trademarks of Scenix Semiconductor, Inc. I2CTM is a trademark of Philips Corporation . MicrowireTM is a trademark of National Semiconductor Corporation All other trademarks mentioned in this document are property of their respective companies.
(c) 2000 Scenix Semiconductor, Inc. All rights reserved.
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SX52BD100
Table of Contents
1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 The Virtual Peripheral Concept . . . . . . . . 4 1.3.2 The Communications Controller . . . . . . . 4 1.4 Programming and Debugging Support . . . . . . . . . . 4 1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Reading and Writing the Ports . . . . . . . . . . . . . . . . . 8 3.2 Read-Modify-Write Considerations . . . . . . . . . . . . 11 3.3 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 MODE Register . . . . . . . . . . . . . . . . . . . 11 3.3.2 Port Configuration Registers . . . . . . . . . 13 3.3.3 Port Configuration Upon Power-Up . . . . 13 Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 PC Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 STATUS Register (03h) . . . . . . . . . . . . . . . . . . . . . 14 4.3 OPTION Register . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 DEVICE CONFIGURATION REGISTERS . . . . . . . 15 4.5 SX48/52BD100 FUSE Word (Read/Program via programming command) . . . . . . . . . . . . . . . . . . . . 16 4.6 SX48/52BD100 FUSEX Word (Read/Program via Programming Command) . . . . . . . . . . . . . . . . . . . 17 4.7 DEVICE Word (Hard-Wired Read-Only Via Programming Command)- Part ID Code . . . . . . . . 17 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 Program Counter . . . . . . . . . . . . . . . . . . 18 5.1.2 Subroutine Stack . . . . . . . . . . . . . . . . . . 18 5.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 Addressing Modes/FSR . . . . . . . . . . . . . 18 5.2.2 Register Access Examples . . . . . . . . . . 20 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Multi-Input Wakeup . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Port B MIWU/Interrupt Configuration . . . . . . . . . . . 22 Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 XT, LP or HS modes . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 External RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 Internal RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Real Time Clock/Counter (RTCC)/Watchdog Timer . . . . . . 27 9.1 RTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3 The Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Product 1.1 1.2 1.3 10.0 Multi-Function Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 10.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . .29 10.1.1 PWM Mode . . . . . . . . . . . . . . . . . . . . . .29 10.1.2 Software Timer Mode . . . . . . . . . . . . . . .29 10.1.3 External Event Mode . . . . . . . . . . . . . . .29 10.1.4 Capture/Compare Mode . . . . . . . . . . . . .30 10.2 Timer Pin Assignments . . . . . . . . . . . . . . . . . . . . .30 10.3 Timer Control Registers . . . . . . . . . . . . . . . . . . . . .30 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Brown-Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register States Upon Different Reset Conditions . . . . . . .38 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 15.1 Instruction Set Features . . . . . . . . . . . . . . . . . . . . .39 15.2 Instruction Execution . . . . . . . . . . . . . . . . . . . . . . .39 15.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . .40 15.4 The Bank Instruction . . . . . . . . . . . . . . . . . . . . . . .40 15.5 Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .40 15.6 Input/Output Operation . . . . . . . . . . . . . . . . . . . . . .40 15.6.1 Read-Modify-Write Considerations . . . .40 15.7 Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . .40 15.8 Loop Counting and Data Pointing Testing . . . . . . .40 15.9 Branch and Loop Call Instructions . . . . . . . . . . . . .41 15.9.1 Jump Operation . . . . . . . . . . . . . . . . . . .41 15.9.2 Page Jump Operation . . . . . . . . . . . . . .41 15.9.3 Call Operation . . . . . . . . . . . . . . . . . . . .41 15.9.4 Page Call Operation . . . . . . . . . . . . . . . .41 15.10 Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . .41 15.11 Subroutine Operation . . . . . . . . . . . . . . . . . . . . . . .42 15.11.1 Push Operation . . . . . . . . . . . . . . . . . . .42 15.11.2 Pop Operation . . . . . . . . . . . . . . . . . . . .42 15.12 Comparison and Conditional Branch Instructions .43 15.13 Logical Instruction . . . . . . . . . . . . . . . . . . . . . . . . .43 15.14 Shift and Rotate Instructions . . . . . . . . . . . . . . . . .43 15.15 Complement and SWAP . . . . . . . . . . . . . . . . . . . .43 15.16 Key to Abbreviations and Symbols . . . . . . . . . . . . .43 Instruction Set Summary Table . . . . . . . . . . . . . . . . . . . . . .44 16.1 Equivalent Assembler Mnemonics . . . . . . . . . . . . .47 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .48 17.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .48 17.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .49 17.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .50 17.4 Comparator DC and AC Specifications . . . . . . . . .50 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.0
3.0
11.0 12.0 13.0 14.0 15.0
4.0
5.0
16.0 17.0
6.0
7.0 8.0
18.0
9.0
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SX52BD100
1.2
Key Features
100 MIPS Performance * DC - 100 MHz operation * 10 ns instruction cycle, 30 ns internal interrupt response at 100 MHz * 1 instruction per clock (branches 3) EE/FLASH Program Memory ad SRAM Data Memory * Access time of < 10 ns provides single cycle access * EE/Flash rated for > 10,000 rewrite cycles * 4096 Words of EE/Flash program memory * 262x8 bits SRAM data memory CPU Features * Compact instruction set * All instructions are single cycle except branch * Eight-level push/pop hardware stack for subroutine linkage * Fast table lookup capability through run-time readable code (IREAD instruction) * Predictable program execution flow for hard real-time applications Fast and Deterministic Interrupt * Jitter-free 3-cycle internal interrupt response * Hardware context save/restore of key resources such as PC, W, STATUS, and FSR within the 3-cycle interrupt response time * External wakeup/interrupt capability on Port B (8 pins) Flexible I/O * All pins individually programmable as I/O * Inputs are TTL or CMOS level selectable * All pins have selectable internal pull-ups * Selectable Schmitt Trigger inputs on Ports B, C, D, and E * All outputs capable of sourcing/sinking 30 mA * Port A outputs have symmetrical drive * Analog comparator support on Port B (RB0 OUT, RB1 IN-, RB2 IN+) * Selectable I/O operation synchronous to the oscillator clock
Hardware Peripheral Features * Two 16-bit timers with 8-bit prescalers supporting: - Software Timer mode - PWM mode - Simultaneous PWM/Capture mode - External Event mode * One 8-bit Real Time Clock/Counter (RTCC) with programable 8-bit prescaler * Watchdog Timer (shares the RTCC prescaler) * Analog comparator * Brown-out detector * Multi-Input Wakeup logic on 8 pins * Internal RC oscillator with configurable rate from 31.25 kHz to 4 MHz * Power-On-Reset Packages * 52-pin PQFP Programming and Debugging Support * On- chip in-system programming support with serial or parallel interface * In-system serial programming via oscillator pins * On-chip in-System debugging support logic * Real-time emulation, full program debug, and integrated development environment offered by third party tool vendors Software Support * Library of off-the-shelf Virtual Peripheral modules * Examples of Virtual Peripheral integration * Evaluation Kits for communication intensive applications
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SX52BD100
1.3
Architecture
The SX devices use a modified Harvard architecture. This architecture uses two separate memories with separate address buses, one for the program and one for data, while allowing transfer of data from program memory to SRAM. This ability allows accessing data tables from program memory. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped with a multi-stage pipeline, which means the next instruction can be fetched from program memory while the current instruction is being executed using data from the data memory. Scenix has developed a revolutionary RISC-based architecture and memory design techniques that is 20 times faster than conventional MCUs, deterministic, jitter free, and totally reprogramable. The SX family implements a four-stage pipeline (fetch, decode, execute, and write back), which results in execution of one instruction per clock cycle. At the maximum operating frequency of 100 MHz, instructions are executed at the rate of one per 10-ns clock cycle. 1.3.1 The Virtual Peripheral Concept Virtual Peripheral concept enables the "software system on a chip" approach. Virtual Peripheral, a software module that replaces a traditional hardware peripheral, takes advantage of the Scenix architecture's high performance and deterministic nature to produce same results as the hardware peripheral with much greater flexibility. The speed and flexibility of the Scenix architecture complemented with the availability of the Virtual Peripheral library, simultaneously address a wide range of engineering and product development concerns. They decrease the product development cycle dramatically, shortening time to production to as little as a few days. Scenix's time-saving Virtual Peripheral library gives the system designers a choice of ready-made solutions, or a head start on developing their own peripherals. So, with Virtual Peripheral modules handling established functions, design engineers can concentrate on adding value to other areas of the application. The concept of Virtual Peripheral combined with in-system re-programmability provides a powerful development platform ideal for the communications industry because of the numerous and rapidly evolving standards and protocols. Overall, the concept of Virtual Peripheral provides benefits such as using a more simple device, reduced component count, fast time to market, increased flexibility in design, customization to your application and ultimately overall system cost reduction. Some examples of Virtual Peripheral modules are: * Communication interfaces such as I2CTM, MicrowireTM (-Wire), SPI, IrDA Stack, UART, and Modem functions * Internet Connectivity protocols such as UDP, TCP/IP stack, HTTP, SMTP, POP3 * Frequency generation and measurement * PPM/PWM generation
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* Delta/Sigma ADC * DTMF generation/detection * FFT/DFT based algorithms 1.3.2 The Communications Controller The combination of the Scenix hardware architecture and the Virtual Peripheral concept create a powerful, creative platform for the communications design communities: SX52BD100 communications controller. Its high processing power, re-cofigurability, cost-effectiveness, and overall design freedom give the designer the power to build products for the future with the confidence of knowing that they can keep up with innovation in standards and other areas.
1.4
Programming and Debugging Support
The SX devices are currently supported by third party tool vendors. On-chip in-system debug capabilities have been added, allowing tools to provide an integrated development environment including editor, macro assembler, debugger, and programmer. Un-obtrusive in-system programming is provided through the OSC pins. For emulation purposes, there is no need for a bond-out chip, so the user does not have to worry about the potential variations in electrical characteristics of a bond-out chip and the actual chip used in the target application. The user can test and revise the fully debugged code in the actual SX, in the actual application, and get to production much faster.
1.5
Applications
Emerging applications and advances in existing ones require higher performance while maintaining low cost and fast time-to-production. The SX device provides solutions for many familiar applications such as process controllers, electronic appliances/tools, security/monitoring systems, consumer automotive, sound generation, motor control, and personal communication devices. In addition, the device is suitable for applications that require DSP-like capabilities, such as closed-loop servo control (digital filters), digital answering machines, voice notation, interactive toys, and magnetic-stripe readers. Furthermore, the growing Virtual Peripheral library features new components, such as the Internet Protocol stack, and communication interfaces, that allow design engineers to embed Internet connectivity into all of their products at extremely low cost and very little effort. Scenix's complete network connectivity protocol stack implementation (SX-Stack), enables single-chip Web servers and E-mail appliances in embedded applications. The implementation includes the physical layer interface with the TCP/IP network connectivity protocols, enabling system designers to produce cost-effective embedded Internet devices without external physical access or a gateway PC.
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SX52BD100
2.0 2.1
CONNECTION DIAGRAMS Pin Assignments
RA6 RA7 MCLR OSC1 OSC2 Vdd Vss RA0 RA1 RA2 RA3 RB0 RB1
_ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 52 - PIN PQFP 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 RB2 RB3 RB4 RB5 RB6 RB7 Vdd Vss RC0 RC1 RC2 RC3 RC4 Top View (c) 2000 Scenix Semiconductor, Inc. All rights reserved. -5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ RD7 RD6 RD5 RD4 Vss Vdd RD3 RD2 RD1 RD0 RC7 RC6 RC5
RA5 RA4 RTCC Vss Vdd RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
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SX52BD100
2.2
Pin Descriptions
Input Levels TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST TTL/CMOS/ST ST ST ST CMOS
Description Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; symmetrical source / sink capability Bidirectional I/O Pin; comparator output; MIWU input Bidirectional I/O Pin; comparator negative input; MIWU input Bidirectional I/O Pin; comparator positive input; MIWU input Bidirectional I/O Pin; MIWU input Bidirectional I/O Pin; MIWU input, Timer T1 Capture Input 1 Bidirectional I/O Pin; MIWU input, Timer T1 Capture Input 2 Bidirectional I/O Pin; MIWU input, Timer T1 PWM/Compare Output Bidirectional I/O Pin; MIWU input, Timer T1 External Event Counter Input Bidirectional I/O pin, Timer T2 Capture Input 1 Bidirectional I/O pin, Timer T2 Capture Input 2 Bidirectional I/O pin, Timer T2 PWM/Compare Output Bidirectional I/O pin, Timer T2 External Event Counter Input Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Bidirectional I/O pin Input to Real-Time Clock/Counter Master Clear reset input - active low Crystal oscillator input - external clock source input Crystal oscillator output - in R/C mode, internally pulled to Vdd through weak pull-up Vdd P - Positive supply pins (a total of four positive supply pins, one on each side of the device) Vss P - Ground pins (a total of four ground pins, one on each side of the device) Note:I = input, O = output, I/O = Input/Output, P = Power, TTL = TTL input, CMOS = CMOS input, ST = Schmitt Trigger input, MIWU = Multi-Input Wakeup input
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Name Pin Type RA0 I/O RA1 I/O RA2 I/O RA3 I/O RA4 I/O RA5 I/O RA6 I/O RA7 I/O RB0 I/O RB1 I/O RB2 I/O RB3 I/O RB4 I/O RB5 I/O RB6 I/O RB7 I/O RC0 I/O RC1 I/O RC2 I/O RC3 I/O RC4 I/O RC5 I/O RC6 I/O RC7 I/O RD0 I/O RD1 I/O RD2 I/O RD3 I/O RD4 I/O RD5 I/O RD6 I/O RD7 I/O RE0 I/O RE1 I/O RE2 I/O RE3 I/O RE4 I/O RE5 I/O RE6 I/O RE7 I/O RTCC I MCLR I OSC1/In/Vpp I OSC2/Out O
SX52BD100
2.3
Part Numbering
Table 2-1. Ordering Information Device SX52BD100/PQ Pins 52 I/O 40 EE/Flash (Words) 4K RAM (Bytes) 262
SX52BDXX-I/PQ
Package Type Extended Temperature Speed Program Memory Size Feature Set Pin Count SceniX
A= B= C= D= Blank = 75 = 100 = TQ = PQ = Tiny PQFP PQFP
Blank = I=
0C to +70C -40C to +85C
50 MHz 75 MHz 100 MHz
512 word 1k word 2k word 4k word
Figure 2-1. Part Number Reference Guide
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SX52BD100
3.0
PORT DESCRIPTIONS 3.1 Reading and Writing the Ports
The five ports are memory-mapped into the data memory address space. To the CPU, the five ports are available as the RA, RB, RC, RD, and RE file registers at data memory addresses 05h through 09h, respectively. Writing to a port data register sets the voltage levels of the corresponding port pins that have been configured to operate as outputs. Reading from a data register reads either the voltage levels of the corresponding port pins or the data contained in the port data register depending on the status PORTRD bit contained in the T2CNTB register.
The device contains five 8-bit I/O ports (Port A through Port E). Port A provides symmetrical drive capability. Each port has four associated 8-bit registers (Direction, Data, TTL/CMOS Select, and Pull-Up Enable) to configure each port pin as Hi-Z input or output, to select TTL or CMOS voltage levels, and to enable/disable the weak pull-up resistor. The least significant bit of the registers corresponds to the least significant port pin. To access these configuration registers, an appropriate value must be written into the MODE register. Upon power-up, all bits in these registers are initialized to "1". The associated registers allow for each port bit to be individually configured under software control as shown below: Table 3-1. Port Configuration Data Direction Registers: RA, RB, RC, RD, RE 0 Output 1 Hi-Z Input TTL/CMOS Select Registers: LVL_A, LVL_B, LVL_C, LVL_D, LVL_E 0 CMOS 1 TTL Pullup Enable Registers: PLP_A, PLP_B, PLP_C, PLP_D, PLP_E 0 1 Enable Disable
Ports B, C, D, and E have additional associated registers (Schmitt-Trigger Enable Registers ST_B and ST_C) to enable or disable the Schmitt Trigger function on each individual port pin as indicated in table below. Table 3-2. Schmitt Trigger Select Schmitt Trigger Enable Registers: ST_B, ST_C, ST_D, ST_E 0 Enable 1 Disable
Port B also supports the on-chip differential comparator. Ports RB1 and RB2 are the comparator negative and positive inputs, respectively, while Port RB0 is the comparator output pin. Port B also supports the Multi-Input Wakeup feature on all eight pins. Port B and Port C also support the multi-function timers T1 and T2. RB4 and RB5 are the T1 capture inputs, RB6 is the T1 PWM output, and RB7 is the T1 external event counter input. Similarly, RC0 and RC1 are the T2 capture inputs, RC2 is the T2 PWM output, and RC3 is the T2 external event counter input. Figure 3-1 shows the internal hardware structure and configuration registers for each pin of Port A. Figure 3-2 shows the same for each pin of Port B, C, D, or E.
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SX52BD100
MODE Mode 0F/1F Mode 0E/1E Mode 0D/1D
RD/WR
RA Direction 0 = Output 1 = Hi-Z Input
Vdd
Pullup (~20k)
Internal Data Bus
RD/WR
PLP_A
0 = Pullup Enable 1 = Pullup Disable
RD/WR
RA Data Port A PIN
RD/WR
LVL_A 0 = CMOS Levels 1 = TTL Levels RD Port A INPUT TTL Buffer M U CMOS Buffer X
Figure 3-1. Port A Configuration
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SX52BD100
MODE Mode 0F/1F Mode 0E/1E Mode 0D/1D Mode 0C/1C
Vdd
RD/WR RB/RC/RD/RE Direction 0 = Output 1 = Hi-Z Input RD/WR
Pullup Resistor (~20k)
PLP_B/C/D/E
0 = Pullup Enable 1 = Pullup Disable
Internal Data Bus
RD/WR
RB/RC/RD/RE Data
Port Pin
RD/WR
LVL_B/C/D/E 0 = CMOS Levels 1 = TTL Levels
RD/WR
ST_B/C/D/E 0 = Schmitt Trigger Enable 1 = Schmitt Trigger Disable RD M U X
TTL Buffer M U CMOS Buffer X
~ ~
Schmitt Trigger Buffer
Port B: Input, MIWU, Comparator, Timer T1 Port C: Input, Timer T2 Port D and E: Input only
Figure 3-2. Port B, Port C, Port D, Port E Configuration For example, suppose all four Port A pins are configured as outputs. To make RA0 and RA1 high and the remaining Port A pins low, you could use the following code:
mov mov W,#$03 $05,W ;load W with the value 03h ;(bits 0 and 1 high) ;write 03h to Port A data ;register
The second "mov" instruction in this example writes the Port A data register (RA), which controls the output levels of the Port A pins, RA0 through RA7. Note that Port A has only four I/O pins in the 48-pin version of the device, in which case only the four least significant bits of this register are used. When a write is performed to a port bit position that has been configured as an input, a write to the port data register is still performed, but it has no immediate effect on the pin. If later that pin is configured to operate as an output, it will reflect the value that has been written to the data register.
In the default device configuration, when a read is performed from a port bit position, the operation is actually reading the voltage level on the pin itself, not necessarily the bit value stored in the port data register. This is true whether the pin is configured to operate as an input or an output. Therefore, with the pin configured to operate as an input, the data register contents have no effect on the value that you read. With the pin configured to operate as an output, what is read generally matches what has been written to the register. PORTRD of the T2CNT2 register determines how the device reads data from its I/O ports (Port A through Port E). Clear this bit to 0 to have the device read data from the port I/O pins directly. Set this bit to 1 to have the device read data from the port data registers. Under normal conditions, it should not matter which method you use to read the port data. However, if a port pin is configured as an output and an external circuit forces the pin to the opposite value, the value read from the port will depend on the reading mode used. Note that this control bit is not related to multi-function timers T1 and T2.
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3.2
Read-Modify-Write Considerations
When two successive instructions are used on the same I/O port (except "mov Rx, W") with a very high clock rate, the "write" part of one instruction might not occur soon enough before the "read" part of the very next instruction, resulting in getting "old" data for the second instruction. To ensure predictable results, avoid using two successive read-modify-write instructions that access the same port data register if the clock rate is high or, insert a single NOP instruction between the successive read-modify-write instructions (if SYNC bit in the FUSE register is enabled, 2 NOP instructions are required). If bit 7 of the T2CNTB (PORTRD) is set, the port read opeartion operation reads data from the data register instead of port pins. In this case, the NOP instructions are not required.
3.3.1 MODE Register The MODE register controls access to the port configuration registers and Timer T1/T2 control registers. Because the MODE register is not memory-mapped, it is accessed by the following special-purpose instructions: * mov M, #lit (move literal to lower 4-bits of MODE register) * mov M,W (move W to lower 5-bits of MODE register) * mov W,M (move MODE register to W) The value contained in the MODE register determines which port control register is accessed by the "mov !rx,W" instruction as indicated in Table 3-3. (The table also shows the timer control registers accessed according to the MODE register setting.) MODE register values not defined in the table are reserved for future expansion and should not be used. Upon power-up, the MODE register is initialized to 1Fh, which enables write access to the port direction control registers. When bit 4 of the MODE register is 0 (the top half of Table 3-3), a "mov !rx,W" instruction moves the contents of the applicable control register into W. When bit 4 of the MODE register is 1 (the bottom half of Table 3-3), a "mov !rx,W" instruction moves the contents of W into the applicable control register. However, there are some exceptions to this. For the CMP_B and WKPND_B registers, the CPU does an exchange of data between W and the control register, regardless of the state of bit 4 in the MODE register. For the WKED_B and WKEN_B registers, the CPU moves the data from W to the control register, regardless of the state of bit 4 in the MODE register. After a value is written to the MODE register, that setting remains in effect until it is changed by writing to the MODE register again. For example, you can write the value 1Eh to the MODE register just once, and then write to each of the five pullup configuration registers using the five "mov !rx,W" instructions.
3.3
Port Configuration
Each port pin offers the following configuration options: * data direction * input voltage levels (TTL or CMOS) * pullup type (enable or disable) * Schmitt trigger input (except for Port A) Port B offers the additional option to use the port pins for the Multi-Input Wakeup/Interrupt function, the analog comparator function, or Timer T1 I/O. Port C offers the additional option to use the port pins for Timer T2 I/O. Port configuration is performed by writing to a set of control registers associated with the port. A special-purpose instruction is used to write these control registers: * mov !RA,W (move W to/from Port A control register) * mov !RB,W (move W to/from Port B control register) * mov !RC,W (move W to/from Port C control register) * mov !RD,W (move W to/from Port D control register) * mov !RE,W (move W to/from Port E control register) Each one of these instructions reads or writes a port control register for Port A, B, C, D, or E. There are multiple control registers for each port. To specify which one you want to access, you use another register called the MODE register.
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Table 3-3. Mode Register Settings MODE Reg. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh mov !RB,W Read T1CPL Read T1CPH Read T1R2CML Read T1R2CMH Read T1R1CML Read T1R1CMH Read T1CNTB Read T1CNTA Exchange CMP_B with W Exchange WKPND_B with W Write WKED_B Write WKEN_B Read ST_B Read LVL_A Read LVL_B Read PLP_A Read PLP_B Read RA Direction Read RB Direction Clear Timer T1 Write T1R2CML Write T1R2CMH Write T1R1CML Write T1R1CMH Write T1CNTB Write T1CNTA Exchange CMP_B with W Exchange WKPND_B with W Write WKED_B Write WKEN_B Write ST_B Write LVL_A Write LVL_B Write PLP_A Write PLP_B Write RA Direction Write RB Direction mov !RA,W mov !RC,W Read T2CPL Read T2CPH Read T2R2CML Read T2R2CMH Read T2R1CML Read T2R1CMH Read T2CNTB Read T2CNTA mov !RD,W mov !RE,W
Read ST_C Read LVL_C Read PLP_C Read RC Direction Clear Timer T2 Write T2R2CML Write T2R2CMH Write T2R1CML Write T2R1CMH Write T2CNTB Write T2CNTA
Read ST_D Read LVL_D Read PLP_D Read RD Direction
Read ST_E Read LVL_E Read PLP_E Read RE Direction
Write ST_C Write LVL_C Write PLP_C Write RC Direction
Write ST_D Write LVL_D Write PLP_D Write RD Direction
Write ST_E Write LVL_E Write PLP_E Write RE Direction
The following code example shows how to program the pullup control registers.
mov mov mov mov mov mov mov mov W,#$1E M, W W,#$03 !RA,W W,#$FF !RB,W W,#$00 !RC,W ;MODE=1Eh to write port pullup ;registers ;W = 0000 0011 ;disable pullups for A0 and A1 ;W = 1111 1111 ;disable all pullups for B0-B7 ;W = 0000 0000 ;enable all pullups for C0-C7
First the MODE register is loaded with 1Eh to select write access to the pullup control registers (PLP_A, PLP_B, and so on). Then the MOV !rx,W instructions are used to specify which port pins are to be connected to the internal pullup resistors. Setting a bit to 1 disconnects the corresponding pullup resistor, and clearing a bit to 0 connects the corresponding pullup resistor.
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3.3.2 Port Configuration Registers The port configuration registers that you control with the MOV !rx,W instruction operate as described below. RA through RE Data Direction Registers (MODE=1Fh) Each register bit sets the data direction for one port pin. Set the bit to 1 to make the pin operate as a high-impedance input. Clear the bit to 0 to make the pin operate as an output. PLP_A through PLP_E: Pullup Enable Registers (MODE=1Eh) Each register bit determines whether an internal pullup resistor is connected to the pin. Set the bit to 1 to disconnect the pullup resistor or clear the bit to 0 to connect the pullup resistor. LVL_A through LVL_E: Input Level Registers (MODE=1Dh) Each register bit determines the voltage levels sensed on the input port, either TTL or CMOS, when the Schmitt trigger option is disabled. Program each bit according to the type of device that is driving the port input pin. Set the bit to 1 for TTL or clear the bit to 0 for CMOS. ST_B through ST_E: Schmitt Trigger Enable Registers (MODE=1Ch) Each register bit determines whether the port input pin operates with a Schmitt trigger. Set the bit to 1 to disable Schmitt trigger operation and sense either TTL or CMOS voltage levels; or clear the bit to 0 to enable Schmitt trigger operation. WKEN_B: Wakeup Enable Register (MODE=1Bh) Each register bit enables or disables the Multi-Input Wakeup/Interrupt (MIWU) function for the corresponding Port B input pin. Clear the bit to 0 to enable MIWU operation or set the bit to 1 to disable MIWU operation. For more information on using the Multi-Input Wakeup/Interrupt function, see Section 7.0.
WKED_B: Wakeup Edge Register (MODE=1Ah) Each register bit selects the edge sensitivity of the Port B input pin for MIWU operation. Clear the bit to 0 to sense rising (low-to-high) edges. Set the bit to 1 to sense falling (high-to-low) edges. WKPND_B: Wakeup Pending Flag Register (MODE=19h) When you access the WKPND_B register using MOV !RB,W, the CPU does an exchange between the contents of W and WKPND_B. Each bit read from the WKPND_B register indicates the status of the corresponding MIWU pin. A bit set to 1 indicates that a valid edge has occurred on the corresponding MIWU pin, and has triggered a wakeup or interrupt. A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. CMP_B: Comparator Register (MODE=08h) When you access the CMP_B register using MOV !RB,W, the CPU does an exchange between the contents of W and CMP_B. This feature lets you read the CMP_B register contents while writing a new value to the register. Clear bit 7 to enable operation of the comparator. Clear bit 6 to place the comparator result on the RB0 pin. Bit 0 is a result flag that is set to 1 when the voltage on RB2 (positive input) is greater than RB1 (negative input), or cleared to 0 otherwise. (For more information on using the comparator, see Section 11.0.) 3.3.3 Port Configuration Upon Power-Up Upon power-up, all the port control registers are initialized to FFh. Thus, each port pin is configured to operate as a high-impedance input that senses TTL voltage levels, with no internal pullup resistor connected. The MODE register is initialized to 1Fh, which allows immediate write access to the data direction registers using the "MOV !rx,W" instruction.
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4.0
SPECIAL-FUNCTION REGISTERS
The CPU uses a set of special-function registers to control operation of the device. The CPU registers include an 8-bit working register (W), which serves as a pseudo accumulator. It holds the second operand of an instruction, receives the literal in immediate type instructions, and also can be programselected as the destination register. A set of 31 file registers serves as the primary accumulator. One of these registers holds the first operand of an instruction and another can be program-selected as the destination register. The first 10 file registers include the Real-Time Clock/Counter register (RTCC), the lower eight bits of the 12-bit Program Counter (PC), the 8-bit STATUS register, five port control registers for Ports A through E, the 8-bit File Select Register (FSR), and INDF (used for indirect addressing). The five low-order bits of the FSR register select one of the 31 file registers in the indirect addressing mode. Calling for the file register located at address 00h (INDF) in any of the file-oriented instructions selects indirect addressing, which uses the FSR register. It should be noted that the file register at address 00h is not a physically implemented register. The CPU also contains an 8level, 12-bit hardware push/pop stack for subroutine linkage. Table 4-1. Special-Function Registers Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Name INDF RTCC PC STATUS FSR RA RB RC RD RE Function Used for indirect addressing Real Time Clock/Counter Program Counter (low byte) Holds Status bits of ALU File Select Register Port RA data register Port RB data register Port RC data register Port RD data register Port RE data register
STATUS register with a result that is different than intended. PA2 Bit 7 000 = Page 0 (000h - 1FFh) 001 = Page 1 (200h - 3FFh) ... 111 = Page 7 (E00h - FFFh) Bit 4: Time Out bit, TO 1 = Set to 1 after power up and upon execution of CLRWDT or SLEEP instructions 0 = A watchdog time-out occurred Bit 3: Power Down bit, PD 1= Set to a 1 after power up and upon execution of the CLRWDT instruction 0 = Cleared to a `0' upon execution of SLEEP instruction Bit 2: Zero bit, Z (affected by most logical, arithmetic, and data movement instructions 1 = Result of math operation is zero 0 = Result of math operation is non-zero Bit 1: Digit Carry bit, DC After Addition: 1 = A carry from bit 3 occurred 0 = No carry from bit 3 occurred After Subtraction: 1 = No borrow from bit 3 occurred 0 = A borrow from bit 3 occurred Bit 0: Carry bit, C After Addition: 1 = A carry from bit 7 of the result occurred 0 = No carry from bit 7 of the result occured. After Subtraction: 1 = No borrow from bit 7 of the result occurred 0 = A borrow from bit 7 of the result occurred Rotate (RR or RL) Instructions: The carry bit is loaded with the low or high order bit, respectively When CF bit of the FUSEX register is cleared to 0, Carry bit works as input for ADD and SUB instructions. PA1 PA0 TO PD Z DC C Bit 0
Bit 7-5: Program memory page select bits PA2:PA0
4.1
PC Register (02h)
The PC register holds the lower eight bits of the program counter. It is accessible at run time to perform branch operations. The upper three bits are located in the STATUS register (PA2:0), bit 8 is not accessible.
4.2
STATUS Register (03h)
The STATUS register holds the arithmetic status of the ALU, the page select bits, and the reset state. The STATUS register is accessible during run time, except that bits PD and TO are read-only. It is recommended that only SETB and CLRB instructions be used on this register. Care should be exercised when writing to the STATUS register as the ALU status bits are updated upon completion of the write operation, possibly leaving the
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4.3
RTW Bit 7 .
OPTION Register
RTE _IE RTS RTE _ES PSA PS2 PS1 PS0 Bit 0 Table 4-2. Prescaler Divider Ratios PS2, PS1, PS0 000 001 010 011 100 101 110 111 RTCC Divide Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Watchdog Timer Divide Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 7: RTW
RTCC/W register selection: 0 = Register 01h addresses W 1 = Register 01h addresses RTCC Bit 6: RTE_IE RTCC interrupt enable: 0 = RTCC roll-over interrupt is enabled 1 = RTCC roll-over interrupt is disabled Bit 5: RTS RTCC increment select: 0 = RTCC increments on internal instruction cycle 1 = RTCC increments upon transition on RTCC pin Bit 4: RTE_ES RTCC edge select: 0 = RTCC increments on low-to-high transitions 1 = RTCC increments on high-to-low transitions Bit 3: PSA Prescaler Assignment: 0 = Prescaler is assigned to RTCC, with divide rate determined by PS0PS2 bits 1 = Prescaler is assigned to WDT, and divide rate on RTCC is 1:1 Bits 2-0: PS2-PS0 Prescaler divider (see Table 4-2)
Upon reset, all bits in the OPTION register are set to 1.
4.4
DEVICE CONFIGURATION REGISTERS
The SX device has three registers (FUSE, FUSEX, DEVICE) that control functions such as speed selection for the internal RC oscillator. These registers are not programmable "on the fly" during normal device operation. Instead, the FUSE and FUSEX registers can only be accessed when the SX device is being programmed. The DEVICE register is a read-only, hard-wired register, defined during the manufacturing process.
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4.5
SX52BD100 FUSE WORD (READ/PROGRAM VIA PROGRAMMING COMMAND)
WDTE 2 FOSC1 1 FOSC0 0 11 10 9 8 7 6 5 4 3
Unused SYNC Unused Unused IRC DIV1/IFBD DIV0/FOSC2 XTLBUF_EN CP
Synchronous input enable (this bit synchronizes the signal presented at the input pin to the internal clock through two internal flip-flops). Required to be enabled unless the transition on the input pin is not close to the clock edge. 0= enabled 1= disabled IRC Internal RC oscillator enable 0= enabled - OSC1 is pulled low by weak pulldown, OSC2 is pulled high by weak pullup 1= disabled - OSC1 and OSC2 behave according to FOSC2:FOSC0 DIV1:DIV0 Internal RC oscillator divider (if IRC = 0) 00b = 4 MHz 01b = 1 MHz 10b = 128 KHz 11b = 32 KHz IFBD Internal crystal/resonator oscillator feedback resistor (10M) 0= Internal feedback resistor disable (external feedback required for crystal operation) 1= Internal feedback resistor enabled (valid only when IRC = 1, disabled when IRC = 0) XTLBUF_EN Crystal Buffer enable (disable when not using a crystal to reduce Idd) 0= Crystal Buffer disabled (disable the crystal buffer for 100 MHz operation) 1= Crystal Buffer enabled CP Code protect enable 0= enabled (FUSE, code, and ID memories read back as scrambled data) 1= disabled (FUSE, code, and ID memories can be read normally) WDTE Watchdog timer enable 0= disabled 1= enabled FOSC2:FOSC0 External oscillator configuration (valid when IRC = 1): 000b = LP1 - low power crystal (32KHz) 001b = LP2 - low power crystal/resonator (32KHz - 1MHz) 010b = XT1 - normal crystal/resonator (32KHz - 10MHz) 011b = XT2 - normal crystal/resonator (1MHz - 24MHz) 100b = HS1 - high speed crystal/resonator (1MHz - 30MHz) 101b = HS2 - high speed crystal/resonator (1MHz - 50MHz) 110b = HS3 - high speed crystal/resonator (1MHz - 100MHz) 111b = External RC network - OSC2 is pulled high by a weak pullup (no CLKOUT output)
SYNC
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4.6
SX52BD100 FUSEX WORD (READ/PROGRAM VIA PROGRAMMING COMMAND)
CF 6 BOR1:BOR0 BORTR1:BORTR0 5 4 3 2 DRT1:DRT0 1 0 11 10 9 8 7
IRCTRIM2 SLEEPCLK IRCTRIM1:IRCTRIM0 Unused
IRCTRIM2: IRCTRIM0
SLEEPCLK
CF
BOR1: BOR0
BORTR1: BORTR0
Internal RC Oscillator Trim. This 3-bit field adjusts the operation of the internal RC oscillator to make it operate within the target frequency range of typically 4.0 MHz plus or minus 8%. Parts are shipped from the factory untrimmed. The device relies on the programming tool to provide trimming. 000b = minimum frequency 111b = maximum frequency Sleep Clock Disable. 0= enable operation of the clock during power down mode (to allow fast start-up). 1= disable clock operation during power down mode (to reduce power consumption). Carry Flag ADD/SUB enable 0= carry bit input to ADD and SUB instructions. 1= ADD and SUB without carry Sets the Brown Out Reset threshold voltage 00b = 4.2V 10b = 2.6V 01b = 2.2V 11b = BOR disabled Brown-Out trim bits (parts are shipped out of factory untrimmed). 00b = minimum threshold voltage 11b = maximum threshold voltage Delay Reset Timer (DRT) timeout period. Specifies the time from assertion of reset to start of code execution. 10b = 0.06 msec 11b = 18.4 msec 00b = 60 msec 01b = 960 msec
DRT1:DRT0
4.7
0 11
DEVICE Word (Hard-Wired Read-Only Via Programming Command)- Part ID Code
0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0
4.8
User Code ID
Locations 1000h to 100Fh are allocated for user code ID.
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5.0 5.1
MEMORY ORGANIZATION Program Memory
move the contents of the working register W into file register 0Fh). There are three different addressing modes, called the indirect, direct, and semi-direct modes. The addressing mode used for register access depends on the 5-bit "fr" value used in the instruction: * indirect mode: fr = 00h * direct mode (fr bit 4 = 0): fr = 01h through 0Fh * semi-direct mode (fr bit 4 = 1): fr = 10h through 1Fh Figure 5-1 illustrates the data memory addressing scheme. For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed. FSR is an 8bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data memory for indirect addressing. In this mode, the global register bank and Bank 1 through Bank F are accessible. Bank 0 is not accessible. For direct addressing (fr=01-0F), the value of "fr" itself specifies the register to be accessed, and the FSR register is ignored. For this addressing mode, only the global register bank is accessible. To gain access to any other bank, you must use either indirect or semi-direct addressing. For semi-direct addressing (fr=10-1F), the bank number is selected by the four high-order bits of FSR, and the register within that bank is selected by the four low-order bits of "fr." In other words, the register address is obtained by combining the four high-order bits of FSR with the four low-order bits of "fr". In this addressing mode, the low-order bits of FSR are ignored. Bank 0 through Bank F are accessible, but the global register bank is not accessible. Figure 5-1 shows how register addressing works in the indirect, direct, and semi-direct modes. The 16 global registers are always accessible by direct addressing, regardless of what is contained in the FSR register. The global registers are also accessible with indirect addressing, but they are not accessible with semi-direct addressing. Of the 16 global registers, nine are special-purpose registers (RTCC, PC, STATUS, and so on), and six are general-purpose registers. Location 00 is used for indirect addressing (INDF). All of the registers in Bank 0 though Bank F are general-purpose registers. To change the contents of the FSR register, the program can either write an eight-bit value to the FSR register or use the "bank" instruction. The "bank" instruction writes r bits 4, 5, and 6 in the FSR register. Bit 7 of FSR is used to select the upper or lower "bank" of memory banks. Thus, to change from one upper bank to another, only a single "bank" instruction is required. To change from one upper bank to a lower bank, the "bank" instruction must be followed by "setb FSR.7".
The program memory is organized as 4K, 12-bit wide words. The program memory words are addressed sequentially by a binary program counter. Upon reset, the program counter is initialized with 0FFFh. If there is no branch operation, it will increment to the maximum value possible for the device and roll over and begin again. Internally, the program memory has a semi-transparent page structure. A page is composed of 512 contiguous program memory words. The lower nine bits of the program counter are zeros at the first address of a page and ones at the last address of a page. This page structure has no effect on the program counter. The program counter will freely increment through the page boundaries. 5.1.1 Program Counter The program counter contains the 12-bit address of the instruction to be executed. The lower eight bits of the program counter are contained in the PC register (02h), and the three upper bits are specified by the STATUS register (PA0, PA1, PA2). Bit 8 is not accessible. Changing the STATUS bits is necessary to cause jumps and subroutine calls across program memory page boundaries. Prior to the execution of a branch operation, the user program must initialize the upper bits of the STATUS register to cause a branch to the desired page. An alternative method is to use the PAGE instruction, which automatically causes branch to the desired page, based on the value specified in the operand field. 5.1.2 Subroutine Stack The subroutine stack consists of eight 12-bit save registers. A physical transfer of register contents from the program counter to the stack or vice versa, and within the stack, occurs on all operations affecting the stack, primarily calls and returns. The stack is physically and logically separate from data RAM. The program cannot read or write the stack.
5.2
Data Memory
The data memory is a RAM-based register set consisting of 262 general-purpose registers and nine special-purpose registers. All of these registers are eight bits wide. The data memory is organized into 16 banks, designated Bank 0 through Bank F, each containing 16 registers, plus an additional bank of 16 "global" registers. Because the registers are organized into banks or "files," these memory-mapped registers are called "file registers." 5.2.1 Addressing Modes/FSR Each SX instruction that accesses a data memory register contains a 5-bit field in the instruction opcode that specifies the register to be accessed. The abbreviation "fr" (file register) represents the 5-bit register address designator. For example, the instruction description "mov fr,W" means that a 5-bit value or label must be substituted for "fr" in the instruction, such as "mov $0F,W" (to
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5-Bit "fr" Value of Instruction 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
FSR
Indirect Addressing
FSR bits 7:0 select one of the registers in the global register set or a register in Bank 1 through Bank F. Bank 0 is not accessible. "fr" bits 3:0 select one of 15 registers in the global register set. The FSR register is ignored. Bank 0 through Bank F are not accessible.
0 fr Direct Addressing
00 INDF 01 RTCC 02 PC 03 STATUS 04 FSR 05 RA 06 RB 07 RC 08 RD 09 RE 0A 0B 0C 0D 0E 0F
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
Global Registers User Configured FSR
Bank 0
Bank 1
Bank 2
Bank E
Bank F
Modified by BANK instruction FSR bits 7:4 select one of 16 banks, and "fr" bits 3:0 select one of 16 registers in that bank. The four low-order bits of FSR are ignored. All 256 registers in Bank 0 through Bank F are accessible. The global registers are not accessible.
XXXX
1 fr Semi-Direct Addressing
Figure 5-1. Register Access Modes
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5.2.2 Register Access Examples Here is an example of an instruction that uses direct addressing:
inc $0F ;increment file register 0Fh
Another approach is to set bit 7 of the FSR register individually after the "bank" instruction to address an upper block bank.
bank $80 setb FSR.7 ;set bits in 4, 5, and 6 FSR ;select Bank 8 in FSR
This instruction increments the contents of file register 0Fh in the global register bank. It does not matter what is contained in the FSR register. To gain access to any register outside of the global register bank, it is necessary to use semi-direct or indirect addressing. In that case, you need to make sure that the FSR register contains the correct value for accessing the desired bank. Here are 2 examples that use semi-direct addressing:
mov W,#$F0 mov FSR,W inc $1F ;load W with F0h ;load W into FSR (Bank F) ;increment file register FFh
To change from an upper block to a lower block bank, bit 7 of FSR must be cleared. With indirect addressing, you specify the full 8-bit address of the register using FSR as a pointer. This addressing mode provides the flexibility to access different registers or multiple registers using the same instruction in the program. You invoke indirect addressing by using fr=00h. For example:
mov mov mov mov W,#$F5 $04,W W,#$01 $00,W ;load ;move ;load ;move W with F5h value F5h into FSR W with 01h value 01h into register F5h
Or, to access bank 0,
mov W,#$00 mov FSR,W inc $1F ;load W with 00h ;load W into FSR (Bank 0) ;increment file register 0Fh
In these examples, "FSR" is a label that represents the value 04h, which is the address of the FSR register in the global register bank. Note that the FSR register is itself a memory-mapped global register, which is always accessible using direct addressing. The "banked" data memory is divided into upper and lower blocks, each consisting of 8 banks of data memory. The range for the lower block is from $00 to $7F, while the rage for the upper block is from $80 to $FF. Bit 7 of the FSR is used to select the upper or lower block. The BANK instruction is used to select the bank within that block. To use the "bank" instruction, in the syntax of the assembly language, you specify an 8-bit value that corresponds to the desired bank number. The assembler encodes bits 4, 5, and 6 of the specified value into the instruction opcode and ignores bit 7 and the low-order bits. For example, if another lower bank was being used to increment file register 2Fh, you could use the following instructions:
bank $20 inc $1F ;select Bank 2 in FSR ;increment register 2F
In the second "mov" instruction, FSR is loaded with the desired 8-bit register address. In the fourth "mov" instruction, fr = 00, so the device looks at FSR and moves the result to the register addressed by FSR, which is the register at F5h (Bank F, register number 5). A practical example that uses indirect addressing is the following program, which clears the upper eight registers in the global register bank and the upper 8 registers in all banks from Bank 1 through Bank F:
clr FSR ;clear FSR to 00h (at address 04h) :loop setb FSR.3 ;set FSR bit 3 clr $00 ;clear register pointed to by FSR incsz FSR ;increment FSR and test ;skip jmp if 00h jmp:loop ;jump back and clear next reg.
This program initially clears FSR to 00h. At the beginning of the loop, it sets bit 3 of FSR so that it starts at 08h. The "clr $00" instruction clears the register pointed to by FSR (initially, the file register at 08h in the global register bank). Then the program increments FSR and clears consecutive file registers, always in the upper half of each bank: (08h, 09h, 0Ah... 0Fh, 18h, 19h... FFh). The loop ends when FSR wraps back to 00h. For addresses from 01h through 0Fh, the global register bank is accessed. For higher addresses, Bank 1 through Bank F are accessed. This program does not affect Bank 0, which is not accessible in the indirect addressing mode. Bank 0 can be accessed only using the semidirect mode.
Note that the "bank" instruction only modifies bits 4, 5, and 6 the FSR register. Therefore, to change from a lower block to an upper block bank, the "bank" instruction will not work. Instead, you need to write the whole FSR register using code such as the following:
mov W,#$80 mov FSR,W ;load W with 80h ;select Bank 8 in FSR
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SX52BD100
6.0
POWER DOWN MODE 6.1 Multi-Input Wakeup
Multi-Input Wakeup is one way of causing the device to exit the power down mode. Port B is used to support this feature. The WKEN_B register (Wakeup Enable Register) allows any Port B pin or combination of pins to cause the wakeup. Clearing a bit in the WKEN_B register enables the wakeup on the corresponding Port B pin. If multi-input wakeup is selected to cause a wakeup, the trigger condition on the selected pin can be either rising edge (low to high) or falling edge (high to low). The WKED_B register (Wakeup Edge Select) selects the desired transition edge. Setting a bit in the WKED_B register selects the falling edge on the corresponding Port B. Resetting the bit selects the rising edge. The WKEN_B and WKED_B registers are set to FFh upon reset. Once a valid transition occurs on the selected pin, the WKPND_B register (Wakeup Pending Register) latches the transition in the corresponding bit position. A logic `1' indicates the occurrence of the selected trigger edge on the corresponding Port B pin. The WKPND_B comes up with undefined value upon reset. The user program must clear the WKPND_B register prior to enabling the interrupt. Upon exiting the power down mode, the Multi-Input Wakeup logic causes program counter to branch to the maximum program memory address (same as reset). Figure 6-1 shows the Multi-Input Wakeup block diagram.
The power down mode is entered by executing the SLEEP instruction. In power down mode, only the Watchdog Timer (WDT) is active, if enabled. If the Watchdog Timer is enabled, upon execution of the SLEEP instruction, the Watchdog Timer is cleared, the TO (time out) bit is set in the STATUS register, and the PD (power down) bit is cleared in the STATUS register. There are three different ways to exit from the power down mode: 1. A timer overflow signal from the Watchdog Timer (WDT). 2. A valid transition on any of the Multi-Input Wakeup pins (Port B pins). 3. An external reset input on the MCLR pin. The states of registers (upon wakeup) are described in Section 14.0. To achieve the lowest possible power consumption, the Watchdog Timer should be disabled (the sleep clock should be disabled) and the device should exit the power down mode through the (Multi-Input Wakeup) MIWU pins or an external reset. In addition, the SLEEPCLOCK should be disabled during the power down mode. Bit 11 of the FUSEX can be used to enable (clear bit to 0) the clock operation during the power down mode (to allow fast clock start-up upon exiting the power down mode).
RB7 RB6
RB1
RB0
Port B Configured as Input WKED_B
8 W MODE Internal Data Bus MODE=0B/1B MODE=0A/1A
01 WKPND_B
MODE=09/19
8
Wake-up: Exit Power Down 8 WKEN_B 0 = Enable 1 = Disable Figure 6-1. Multi-Input Wakeup Block Diagram
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SX52BD100
6.2
Port B MIWU/Interrupt Configuration
Here is an example of a program segment that configures the RB0, RB1, and RB2 pins to operate as MultiInput Wakeup/Interrupt pins, sensitive to falling edges:
mov mov mov mov mov mov mov mov W,#$1F M,W W,#$07 !RB,W W,#$1A M,W W,#$07 !RB,W ;prepare to write port data ;direction registers ;load W with the value 07h ;configure RB0-RB2 to be inputs ;prepare to write WKED_B ;(edge) register ;load W with the value 07h ;configure RB0-RB2 to sense ;falling edges ;prepare to access WKPND_B ;(pending) register ;clear W ;clear all wakeup pending flags ;prepare to write WKEN_B (enable) ;register ;load W with the value F8h ;enable RB0-RB2 to operate as ;wakeup inputs
The WKPND_B register comes up with a random value upon reset. The user program must clear the register prior to enabling the wake-up condition or interrupts. The proper initialization sequence is: 1. Select the desired edge (through WKED_B register). 2. Clear the WKPND_B register. 3. Enable the Wakeup condition (through WKEN_B register). Below is an example of how to read the WKPND_B register to determine which Port B pin caused the wakeup or interrupt, and to clear the WKPND_B register:
mov mov clr mov W, #$19 ;prepare to exchange WKPND_B ;with W (can also use $09) M, W W !RB,W
;W contains WKPND_B ;contents of W exchanged ;with contents of WKPND_B
mov mov mov mov mov mov mov mov
W,#$19 M,W W,#$00 !RB,W W,#$1B M,W W,#$F8 !RB,W
The final "mov" instruction in this example performs an exchange of data between the working register (W) and the WKPND_B register. This exchange occurs only with accesses to the WKPND_B and CMP_B registers. Otherwise, the "mov" instruction does not perform an exchange, but only moves data from the source to the destination.
To prevent false interrupts, the enabling step (clearing bits in WKEN_B) should be done as the last step in a sequence of Port B configuration steps. After this program segment is executed, the device can receive interrupts on the RB0, RB1, and RB2 pins. If the device is put into the power down mode (by executing a SLEEP instruction), the device can then receive wakeup signals on those same pins.
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SX52BD100
7.0
INTERRUPT SUPPORT
WKEN_B register enables the interrupt on the corresponding Port B pin. The WKED_B selects the transition edge to be either positive or negative. The WKEN_B and WKED_B registers are set to FFh upon reset. Setting a bit in the WKED_B register selects the falling edge while clearing the bit selects the rising edge on the corresponding Port B pin. The WKPND_B register serves as the external interrupt pending register. The WKPND_B register comes up with a random value upon reset. The user program must clear the WKPND_B register prior to enabling the interrupt.
The device supports both internal and external maskable interrupts. The internal interrupt is generated as a result of the RTCC rolling over from FFh to 00h. This interrupt source has an associated enable bit located in the OPTION register and pending flag bit in the Timer T1 Control B register. In addition, timers T1 and T2 each has three interrupt sources associated with counter overflow, compare match, and input capture. Port B provides the source for eight external software selectable, edge sensitive interrupts, when the device is not in the power down mode. These interrupt sources share logic with the Multi-Input Wakeup circuitry. The WKEN_B register allows interrupt from Port B to be individually enabled or disabled. Clearing a bit in the
Port B PIN WKED_B WKED_B
RTCC Overflow
From MODE (MODE = 0A/1A) WKPND_B In te rn al D a ta B u s WKPND_B
STATUS Register PD Flag
From MODE (MODE = 09/19) 1 = Ext. Interrupt through Port B 0 = Sleep Mode, no Ext. Interrupt RTE_IE OPTION
Interrupt PC, STATUS, FSR, W, MODE 000 Interrupt Stack PC
WKEN_B Device-Specific Interrupt Sources (e.g. Timer T1)
Figure 7-1. Interrupt Structure
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SX52BD100
All interrupts are global in nature; that is, no interrupt has priority over another. Interrupts are handled sequentially. Figure 7-2 shows the interrupt processing sequence. Once an interrupt is acknowledged, all subsequent global interrupts are disabled until return from servicing the current interrupt. The PC is pushed onto the single level interrupt stack, and the contents of the FSR, STATUS, MODE, and W registers are saved in their corresponding shadow registers. The status bits PA2, PA1, and PA0 are cleared after STATUS has been saved in its shadow register. The interrupt logic has its own single-level stack and is not part of the CALL subroutine stack. The vector for the interrupt service routine is address 0. Once in the interrupt service routine, the user program must poll all interrupt pending bits to determine the source of the interrupt. The interrupt service routine should clear the corresponding interrupt pending flag. Normally it is a requirement for the user program to process every interrupt without missing any. To ensure this, the longest path through the interrupt routine must take less time than the shortest possible delay between interrupts. If an external interrupt occurs during the interrupt routine, the pending register will be updated but the trigger will be ignored unless interrupts are disabled at the beginning of the interrupt routine and enabled again at the end. This
also requires that the new interrupt does not occur before interrupts are disabled in the interrupt routine. If an additional interrupt occurs before it can be disabled, the device will miss the interrupt. In other words, using more than one interrupt, such as multiple external interrupts or both RTCC and external interrupts, can result in missed or, at best, jittery interrupt handling should one occur during the processing of another. When handling external interrupts, the interrupt routine should clear at least one pending register bit. The bit that is cleared should represent the interrupt being handled in order for the next interrupt to trigger. Upon return from the interrupt service routine, the contents of PC, FSR, STATUS, MODE, and W registers are restored from their corresponding shadow registers. The interrupt service routine should end with instructions such as RETI or RETIW. RETI pops the interrupt stack and the special shadow registers used for storing W, STATUS, MODE, and FSR (preserved during interrupt handling). RETIW behaves like RETI but also adds W to RTCC. The interrupt return instruction enables the global interrupts. If a MIWU interrupt occurs during a pre-existing interrupt service routine, the MIWU interrupt flag is set immediately, and the MIWU interrupt is serviced upon completion of the pre-existing interrupt service routine.
Program Memory Address 000h
Interrupt Service Routine
PC RETI Interrupt Stack Interrupt Stack 000h PC W Register STATUS Register FSR Register MODE Register W Shadow Register STATUS Shadow Register FSR Shadow Register MODE Shadow Register
PC W Register STATUS Register FSR Register MODE Register W Shadow Register STATUS Shadow Register FSR Shadow Register MODE Shadow Register
Note:The interrupt logic has its own single-level stack and is not part of the CALL subroutine stack. Figure 7-2. Interrupt Processing
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SX52BD100
8.0
OSCILLATOR CIRCUITS
To use an external crystal/resonator network, you connect a crystal or ceramic resonator to the OSC1/CLKIN and OSC2/CLKOUT pins according to the circuit configuration shown in Figure 8-1. A parallel resonant crystal type is recommended. Use of a series resonant crystal may result in a frequency that is outside the crystal manufacturer specifications. For operating frequencies above 50 MHz, HS1 setting must be selected (FOSC2:FOSC0 should contain 100) and external clock oscillators must be used. In such cases, the clock oscillator output can be directly connected to the OSC1 pin and the OSC2 pin should be left open.Table 8-1 shows the recommended component values for associated with crystal-based oscillator. If the XT, LP, or HS mode is selected, the OSC1/CLKIN pin can be driven by an external clock source rather than a resonator network, as long as the clock signal meets the specified duty cycle, rise and fall times, and input levels (Figure 8-2). In this case, the OSC2/CLKOUT pin should be left open.
The device supports several user-selectable oscillator modes. The oscillator modes are selected by programming the appropriate values into the FUSE Word register. These are the different oscillator modes offered: LP: Low Power Crystal XT: Crystal/Resonator HS: High Speed Crystal/Resonator/Clock Oscillator RC: External Resistor/Capacitor Internal Resistor/Capacitor
8.1
XT, LP or HS modes
In XT, LP or HS modes, you can use either an external crystal/resonator network or an external clock signal as the device clock. Table 8-1. External Component Selection for Crystal Oscillator (Vdd = 5.0V) FOSC2:FOSC0 Crystal Frequency 011 011 100 101 101 4 MHz 8 MHz 20 MHz 32 MHz 50 MHz Fundamental
SX Device Internal Circuitry SX Device SLEEPC LK
Setting Symbol XT2 XT2 HS1 HS2 HS3
C1 (pF)
C2 (pF)
RF (M)
Rs (Ohm) IFBD = 0
33 22 22 15 15
56 56 33 47 33
1 1 1 1 1
0 0 0 0 0
OSC1 OSC1 RF XTAL C1 C2 OSC2 RS Externally Generated Clock
OSC2 Open
Figure 8-2. External Clock Input Operation (HS, XT or LP OSC Configuration) Figure 8-1. Crystal Operation (or Ceramic Resonator) (HS, XT or LP OSC Configuration)
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SX52BD100
8.2
External RC Mode
8.3
Internal RC Mode
The external RC oscillator mode provides a cost-effective approach for applications that do not require a precise operating frequency. In this mode, the RC oscillator frequency is a function of the supply voltage, the resistor (R) and capacitor (C) values, and the operating temperature. In addition, the oscillator frequency will vary from unit to unit due to normal manufacturing process variations. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low C values. The external R and C component tolerances contribute to oscillator frequency variation as well. Figure 8-3 shows the external RC connection diagram. The recommended R value is from 3k to 100k. For R values below 2.2k, the oscillator may become unstable, or may stop completely. For very high R values (such as 1 M), the oscillator becomes sensitive to noise, humidity, and leakage. Although the oscillator will operate with no external capacitor (C = 0pF), it is recommended that you use values above 20 pF for noise immunity and stability. With no or small external capacitance, the oscillation frequency can vary significantly due to variation in PCB trace or package lead frame capacitances.
The internal RC mode uses an internal oscillator, so the device does not need any external components. At 4 MHz, the internal oscillator provides typically +/-8% accuracy over the allowed temperature range. The internal clock frequency can be divided down to provide one of eight lower-frequency choices by selecting the desired value in the FUSE Word register. The frequency range is from 31.25 kHz to 4 MHz.The default operating frequency of the internal RC oscillator may not be 4 MHz. This is due to the fact that the SX device requires trimming to obtain 4 MHz operation. The parts shipped out of the factory are not trimmed. The device relies on the programming tool provided by the third party vendors to support trimming. During internal RC mode, OSC1 is high impedance and OSC2 pulled low.
SX Device Internal Circuitry
~
N
OSC1
OSC2
Vdd
R C
Figure 8-3. RC Oscillator Mode
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SX52BD100
9.0 REAL TIME CLOCK/COUNTER (RTCC)/WATCHDOG TIMER
The device contains an 8-bit Real Time Clock/Counter (RTCC) and an 8-bit Watchdog Timer (WDT). An 8-bit programmable prescaler extends the RTCC to 16 bits. If the prescaler is not used for the RTCC, it can serve as a postscaler for the Watchdog Timer. Figure 9-1 shows the RTCC and WDT block diagram.
9.2
Watchdog Timer
The watchdog logic consists of a Watchdog Timer which shares the same 8-bit programmable prescaler with the RTCC. The prescaler actually serves as a postscaler if used in conjunction with the WDT, in contrast to its use as a prescaler with the RTCC. The WDT is clocked by it's own internal RC oscillator.
9.3
The Prescaler
9.1
RTCC
RTCC is an 8-bit real-time timer that is incremented once each instruction cycle or from a transition on the RTCC pin. The on-board prescaler can be used to extend the RTCC counter to 16 bits. The RTCC counter can be clocked by the internal instruction cycle clock or by an external clock source presented at the RTCC pin. To select the internal clock source, bit 5 of the OPTION register should be cleared. In this mode, RTCC is incremented at each instruction cycle unless the prescaler is selected to increment the counter. To select the external clock source, bit 5 of the OPTION register must be set. In this mode, the RTCC counter is incremented with each valid signal transition at the RTCC pin. By using bit 4 of the OPTION register, the transition can be programmed to be either a falling edge or rising edge. Setting the control bit selects the falling edge to increment the counter. Clearing the bit selects the rising edge. The RTCC generates an interrupt as a result of an RTCC rollover from FFh to 00h. Bit 7 of the Timer T1 Control B register is an interrupt pending flag (RTCCOV) associated with this event. The program should read this flag to determine any rollover occurrence. Writing to the RTCC also clears the prescaler if it is assigned to the RTCC (bit 3 at OPTION register is cleared).Using the "TEST fr" with RTCC (with fr being the RTCC and RTCC clock internally or externally) will not allow the RTCC to increment. The workaround is to use the "MOV W, RTCC" instruction instead.
The 8-bit prescaler may be assigned to either the RTCC or the WDT through the PSA bit (bit 3 of the OPTION register). Setting the PSA bit assigns the prescaler to the WDT. If assigned to the WDT, the WDT clocks the prescaler and the prescaler divide rate is selected by the PS0, PS1, and PS2 bits located in the OPTION register. Clearing the PSA bit assigns the prescaler to the RTCC. Once assigned to the RTCC, the prescaler clocks the RTCC and the divide rate is selected by the PS0, PS1, and PS2 bits in the OPTION register. The prescaler is not mapped into the data memory, so run-time access is not possible. The prescaler cannot be assigned to both the RTCC and WDT simultaneously.
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SX52BD100
WDTE (from FUSE Word) WDT
RTCC Interrupt Enable FOSC RTCC pin RTW RTE_IE RST RTE_ES PSA PS2 PS1 PS0 OPTION Register
M U X
MUX 8-Bit Prescaler
MUX (8 to 1) M U X RTCC MUX 8-Bits WDT Timeout Data Bus
RTCC Rollover Interrupt
Interrupt to CPU
Pending Flag (RTCCOV bit in T1CNTB Register, SX52BD100 only)
Figure 9-1. RTCC and WDT Block Diagram
10.0 MULTI-FUNCTION TIMERS
The device contains two independent 16-bit multi-function timers, designated T1 and T2. These versatile, programmable timers reduce the software burden on the CPU in real-time control applications such as PWM generation, motor control, triac control, variable-brightness display control, sine wave generation, and data acquisition. Each timer consists of a 16-bit counter register supported by a dedicated 16-bit capture register and two 16-bit comparison register. The second compare register can also serve as capture register. Each timer uses up to four I/O pins: one clocking input, two capture inputs, and one timer output. The timer I/O pins are alternate functions of Port B pins for timer T1 and Port C pins for Timer T2. Figure 10-1 is a block diagram showing the registers and I/O pins of one timer. The 16-bit free-running timer/counter register is initialized to 0000h upon reset and counts upward continuously. It is clocked either by an external signal provided on an I/O pin or by the onchip system clock divided by a programmable 8-bit prescaler register. The CPU can access the Compare and Capture registers by using the "mov !RB,W" instruction for T1 or the "mov !RC,W" instruction for T2. The other timer registers are not directly accessible. You can configure the timer to generate an interrupt upon overflow from FFFFh to 0000h, upon a match between the counter value and a programmed comparison value, Figure 10-1. Multi-Function Timer Block Diagram
Compare Interrupt Capture 2 Output
match 16-Bit Compare R2/Capture Register2 16-Bit Compare Register R1
System Clock
8-Bit Prescaler
16-Bit Comparator
Ext. Clock MUX 16-Bit Free-Running Timer/Counter Capture Interrupt Capture 1 16-Bit Capture Register 1
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SX52BD100
or upon the occurrence of a valid capture signal on either of two capture inputs. The timers can be reset by writing to the registers accessed via MODE address $10.
10.1 Timer Operating Modes
Each timer can be configured to operate in one of the following modes: * * * * Pulse Width Modulation (PWM) mode Software Timer mode External Event mode Capture/Compare mode
10.1.2 Software Timer Mode The Software Timer mode is the same as the PWM mode, except that the timer does not toggle the output signal. Instead, the application program takes action in response to the interrupts generated upon each match between the counter and the contents of the active comparison value in either R1 or R2. The software can determine the cause of each interrupt by checking the timer interrupt pending flags. There are different flag bits associated with each type of event (R1 match, R2 match, and overflow). 10.1.3 External Event Mode The External Event mode is the same as the PWM mode, except that the counter register is clocked by an external signal provided on an input pin rather than by the system clock. This mode can be used to count the occurrences of external events. The input pin can be configured to sense either rising or falling edges.
10.1.1 PWM Mode In the Pulse Width Modulation (PWM) mode, the timer generates an output signal having a programmable frequency and duty cycle. To use this mode, you load two 16-bit comparison registers, R1 and R2, with the number of timer clock cycles that you want the output signal to be high and low. The timer starts from zero and counts up until it reaches the value in R1. At that point, it generates an interrupt (if enabled), toggles the output signal, and starts counting from zero again. The second time, it counts up until it reaches the value in R2. At that point, it again generates an interrupt (if enabled), toggles the output signal, and starts counting from zero again. This process is repeated continuously, alternating between R1 and R2 to obtain the value at which to toggle the output signal and return the counter to zero. The values of R1 and R2 establish the duty cycle and frequency of the output signal. If R1 and R2 contain the same value, the resulting output signal is a square wave. In the PWM mode, the timer is clocked by the on-chip system clock divided by an 8-bit prescaler value. The divide-by factor can be set to any power-of-2 from 1 to 256. Thus, the period of the timer clock can be set from 1 to 256 times the system clock period.
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SX52BD100
10.1.4 Capture/Compare Mode In the Capture/Compare mode, the counter counts upward continuously without interruption. A valid transition received on either of two input pins causes the current value of the counter to be captured in an associated capture register. This capture feature can be used to keep track of the elapsed time between successive external events. In addition, the timer continuously compares the counter value against the value programmed into the R1 register. Each time a match occurs, it toggles the timer output pin, and also generates an interrupt (if enabled). The timer continues to count upward after a match occurs (unlike the PWM mode, which resets the counter to zero when a match occurs). In the Capture/Compare mode, the timer is clocked by the on-chip system clock divided by an 8-bit prescaler value. The divide-by factor can be set to any power-of-2 from 1 to 256. The two input capture pins are designated Capture 1 and Capture 2. They can be configured to sense either rising or falling edges. The Capture 1 pin captures the counter value in a dedicated 16-bit capture register, a read-only register. The Capture 2 pin captures the counter value in the R2 register. The occurrence of a capture event also generates an interrupt (if enabled) and sets an associated interrupt pending flag. Overflow of the counter from FFFFh to 0000h also generates an interrupt (if enabled) and sets an associated interrupt pending flag. Because the counter is free-running, an overflow can occur at any time. In cases where the time between successive capture events might exceed 65,536 counts of the timer, the software should keep track of the number of overflows between successive events in order to determine the true amount of time between such events. An occurrence of a match between the counter value and the programmed value in the R1 register toggles the
timer output pin. It also generates an interrupt (if enabled) and sets an associated interrupt pending flag. The timer continues to run freely without being reset to zero. Therefore, if you want to have a fixed timeout period for this interrupt, the interrupt service routine must write a new value into R1 each time a match occurs.
10.2
Timer Pin Assignments
The following table lists the I/O port pins associated with the Timer T1 and Timer T2 I/O functions. Table 10-1. Timer T1/T2 Pin Assignments I/O Pin RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 Timer T1/T2 Function Timer T1 Capture Input 1 Timer T1 Capture Input 2 Timer T1 PWM/Compare Output Timer T1 External Event Clock Source Timer T2 Capture Input 1 Timer T2 Capture Input 2 Timer T2 PWM/Compare Output Timer T2 External Event Clock Source
10.3
Timer Control Registers
There are two 8-bit control registers associated with each timer, called the Control A and Control B registers. The Control A register contains the interrupt enable bits and interrupt flag bits associated with the timer. (Interrupts are caused by comparison, capture, and overflow events.) The Control B register contains bits for setting the timer operating mode, the clock prescaler divide-by factor, and the input signal edge sensitivity. Each Control B register also contains one device configuration bit not related to operation of the multi-function timers. The register formats are shown in the following diagrams.
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SX52BD100
Timer T1 Control A Register (T1CNTA) T1CPF2 7 T1CPF2 T1CPF1 T1CPIE T1CPF1 6 T1CPIE 5 T1CMF2 4 T1CMF1 3 T1CMIE 2 T1OVF 1 T1OVIE 0
T1CMF2
T1CMF1
T1CMIE
T1OVF T1OVIE
Timer T1 Capture Flag 2. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 2 pin of Timer T1 (pin RB5). It stays set until cleared by the software. Timer T1 Capture Flag 1. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 1 pin of Timer T1 (pin RB4). It stays set until cleared by the software. Timer T1 Capture Interrupt Enable. Set this bit to 1 to enable capture interrupts for Timer T1 in Capture/Compare mode. In that case, an interrupt will occur each time a valid edge is received on the Capture 1 or Capture 2 pin of Timer T1. Clear this bit to 0 to disable capture interrupts. Timer T1 Comparison Flag 2. This flag is automatically set to 1 when the contents of the timer counter match the contents of R2, when R2 is the active comparison register. The flag stays set until it is cleared by the software. Timer T1 Comparison Flag 1. This flag is automatically set to 1 when the contents of the timer counter match the contents of R1, when R1 is the active comparison register. The flag stays set until it is cleared by the software. Timer T1 Comparison Interrupt Enable. Set this bit to 1 to enable comparison interrupts for Timer T1. In that case, an interrupt will occur each time the contents of the timer counter match the contents of the active comparison register (R1 or R2) of Timer T1. Clear this bit to 0 to disable comparison interrupts. Timer T1 Overflow Flag. This flag is automatically set to 1 when the timer counter overflows from FFFFh to 0000h. The flag stays set until it is cleared by the software. Timer T1 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T1. In that case, an interrupt will occur each time Timer T1 overflows. Clear this bit to 0 to disable overflow interrupts.
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SX52BD100
Timer T1 Control B Register (T1CNTB) RTCCOV 7 RTCCOV T1CPEDG 6 T1EXEDG 5 4 T1PS2-T1PS0 3 2 T1MC1-T1MC0 1 0
T1CPEDG
T1EXEDG
T1PS2T1PS0
RTCC Overflow Flag. This flag is automatically set to 1 when the Real-Time Clock/Counter (RTCC) overflows from FFh to 00h. This flag stays set until it is cleared by the software. Note that this flag is not related to multi-function timers T1 and T2. Timer T1 Capture Edge. This bit sets the edge sensitivity of the Timer T1 input capture pins, Capture 1 and Capture 2 (RB4 and RB5). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. Timer T1 External Event Clock Edge. This bit sets the edge sensitivity of the Timer T1 input used to count external events (RB7). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. Timer T1 Prescaler Divider field. This 3-bit field specifies the divide-by factor for generating the timer clock from the on-chip system clock: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101= divide by 32 110 = divide by 64 111 = divide by 128 For example, setting this field to 010 sets the divide-by factor to 4, which means that the T1 counter register is incremented once every four system clock cycles. Timer T1 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode
T1MC1T1MC0
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SX52BD100
Timer T2 Control A Register (T2CNTA) T2CPF2 7 T2CPF2 T2CPF1 T2CPIE T2CPF1 6 T2CPIE 5 T2CMF2 4 T2CMF1 3 T2CMIE 2 T2OVF 1 T2OVIE 0
T2CMF2
T2CMF1
T2CMIE
T2OVF T2OVIE
Timer T2 Capture Flag 2. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 2 pin of Timer T2 (pin RC1). It stays set until cleared by the software. Timer T2 Capture Flag 1. In Capture/Compare mode, this flag is automatically set to 1 when a capture event occurs on the Capture 1 pin of Timer T2 (pin RC1). It stays set until cleared by the software. Timer T2 Capture Interrupt Enable. Set this bit to 1 to enable capture interrupts for Timer T2 in Capture/Compare mode. In that case, an interrupt will occur each time a valid edge is received on the Capture 1 or Capture 2 pin of Timer T2. Clear this bit to 0 to disable capture interrupts. Timer T2 Comparison Flag 2. This flag is automatically set to 1 when the contents of the timer counter match the contents of R2, when R2 is the active comparison register. The flag stays set until it is cleared by the software. Timer T2 Comparison Flag 1. This flag is automatically set to 1 when the contents of the timer counter match the contents of R1, when R1 is the active comparison register. The flag stays set until it is cleared by the software. Timer T2 Comparison Interrupt Enable. Set this bit to 1 to enable comparison interrupts for Timer T2. In that case, an interrupt will occur each time the contents of the timer counter match the contents of the active comparison register (R1 or R2) of Timer T2. Clear this bit to 0 to disable comparison interrupts. Timer T2 Overflow Flag. This flag is automatically set to 1 when the timer counter overflows from FFFFh to 0000h. The flag stays set until it is cleared by the software. Timer T2 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T2. In that case, an interrupt will occur each time Timer T2 overflows. Clear this bit to 0 to disable overflow interrupts.
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Timer T2 Control B Register (T2CNTB) PORTRD 7 PORTRD T2CPEDG 6 T2EXEDG 5 4 T2PS2-T2PS0 3 2 T2MC1-T2MC0 1 0
T2CPEDG
T2EXEDG
T2PS2T2PS0
Port Read mode. This bit determines how the device reads data from its I/O ports (Port A through Port E). Clear this bit to 0 to have the device read data from the port I/O pins directly. Set this bit to 1 to have the device read data from the port data registers. Under normal conditions, it should not matter which method you use to read the port data. However, if a port pin is configured as an output and an external circuit forces the pin to the wrong value, the value read from the port will depend on the reading mode used. Note that this control bit is not related to multi-function timers T1 and T2. Timer T2 Capture Edge. This bit sets the edge sensitivity of the Timer T2 input capture pins, Capture 1 and Capture 2 (RC0 and RC1). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. Timer T2 External Event Clock Edge. This bit sets the edge sensitivity of the Timer T2 input used to count external events (RC3). Set this bit to 1 to sense positive-going (low-to-high) edges. Clear this bit to 0 to sense negative-going (high-to-low) edges. Timer T2 Prescaler Divider field. This 3-bit field specifies the divide-by factor for generating the timer clock from the on-chip system clock: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 For example, setting this field to 010 sets the divide-by factor to 4, which means that the T2 counter register is incremented once every four system clock cycles. Timer T2 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode
T2MC1T2MC0
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11.0 COMPARATOR
The device contains an on-chip differential comparator. Ports RB0-RB2 support the comparator. Pins RB1 and RB2 are the comparator negative and positive inputs, respectively, while RB0 serves as the comparator output pin. To use these pins in conjunction with the comparator, the user program must configure RB1 and RB2 as inputs and RB0 as an output. The CMP_B register is used to enable the comparator, to read the output of the comparator internally, and to enable the output of the comparator to the comparator output pin. The comparator enable bits are set to "1" upon reset, thus disabling the comparator. To avoid drawing additional current during the power down mode, the comparator should be disabled before entering the power down mode. Here is an example of how to set up the comparator and read the CMP_B register.
mov W,#$18 mov M,W mov W,#$00 mov !RB,W ... mov W,#$18 mov M,W mov W,#$00 mov !RB,W ;set MODE register to access ;CMP_B ;clear W ;enable comparator and its ;output ;delay after enabling ;comparator for response ;set MODE register to access ;CMP_B ;clear W ;enable comparator and its ;output and also read CMP_B ;(exchange W and CMP_B) and W,#$01 snb $03.2 jmp rb2_hi ... ;set/clear Z flag based on ;comparator result ;test Z flag in STATUS reg ;(0 => RB2RB1
The final "mov" instruction in this example performs an exchange of data between the working register (W) and the CMP_B register. This exchange occurs only with accesses to CMP_B and WKPEND_B. Otherwise, the "mov" instruction does not perform an exchange, but only moves data from the source to the destination. The following figure shows the format of the CMP_B register. CMP_B - Comparator Enable/Status Register CMP_EN Bit 7 CMP_OE Bit 6 Reserved Bits 5-1 CMP_RES Bit 0
CMP_RES
CMP_OE CMP_EN
Comparator result: 1 for RB2>RB1 or 0 for RB2Internal D ata Bus
C M P_B C M P_EN C M P_O E R B0 R B1 R B2 R E S E R V E D C M P_R ES 0 MODE M O D E = 08/18 7 6 W
+
Point to C M P_B
Figure 11-1. Comparator Block Diagram
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12.0 RESET
Power-On-Reset, Brown-Out reset, watchdog reset, wakeup reset, or external reset initializes the device. Each one of these reset conditions causes the program counter to branch to the top of the program memory (FFFh). The device incorporates an on-chip Power-On Reset (POR) circuit that generates an internal reset as Vdd rises during power-up. Figure 12-1 shows the block diagram of the circuit. The circuit contains a 10-bit Delay Reset Timer (DRT) and a reset latch. The DRT controls the reset timeout delay. The reset latch controls the internal reset signal. Upon power-up, the reset latch is set (device held in reset), and the DRT starts counting once it detects a valid logic high signal at the MCLR pin. Once DRT reaches the end of the timeout period (typically 72 msec), the reset latch is cleared, releasing the device from reset state.
MIWU POR POR
use the external RC circuit. The RC delay should exceed the time period it takes Vdd to reach a valid operating voltage. Vdd
MCLR POR Tdrt drt_time_out RESET
Figure 12-2. Time-Out Sequence on Power-Up (MCLR not tied to Vdd)
Vdd
MCLR POR Tdrt drt_time_out
V1
Vdd
BROWN-OUT
MCLR/Vpp pin
wdt_time_out enable 10-Bit Asynch S Ripple Counter (DRT Start-Up R Timer) drt_time _out Q RESET QN
RESET
Figure 12-3. Time-out Sequence on Power-up (MCLR tied to Vdd): Slow Rise Time
rc_clk
Note:Ripple counter is 10 bits for Power on Reset (POR) only. Figure 12-1. Block Diagram of On-Chip Reset Circuit Figure 12-2 shows a power-up sequence where MCLR is not tied to the Vdd pin and Vdd signal is allowed to rise and stabilize before MCLR pin is brought high. The device will actually come out of reset Tdrt msec after MCLR goes high. The brown-out circuitry resets the chip when device power (Vdd) dips below its minimum allowed value, but not to zero, and then recovers to the normal value. Figure 12-3 shows the on-chip Power-On Reset sequence where the MCLR and Vdd pins are tied together. The Vdd signal is stable before the DRT timeout period expires. In this case, the device will receive a proper reset. However, Figure 12-4 depicts a situation where Vdd rises too slowly. In this scenario, the DRT will time-out prior to Vdd reaching a valid operating voltage level (Vdd min). This means the device will come out of reset and start operating with the supply voltage not at a valid level. In this situation, it is recommended that you
D
Vdd
R C
R1 MCLR
Figure 12-4. External Power-On Reset Circuit (For Slow Vdd Power-up) Vdd
MCLR POR Tdrt drt_time_out RESET
Figure 12-5. Time-out Sequence on Power-up (MCLR tied to Vdd): Fast Vdd Rise Time
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A 2-bit field in the FUSEX register can be used to specify the Delay Reset Timer (DRT) timeout period that results in an automatic wake-up from the power down mode: 00 = 0.06 msec 01 = 18.4 msec (default) 10 = 60 msec 11 = 960 msec For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT1:WDRT0 field to 00. This will keep the clock operating during the power down mode and allow a minimum start-up delay. Note 1: The external Power-On Reset circuit is required only if Vdd power-up is too slow. The diode D helps discharge the capacitor quickly when Vdd powers down. Note 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specifications. R1 = 100 to 1k will limit any current flowing into MCLR from external capacitor C. This helps prevent MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
13.0
BROWN-OUT DETECTOR
The on-chip brown-out detection circuitry resets the device when Vdd dips below the specified brown-out voltage. The device is held in reset as long as Vdd stays below the brown-out voltage. The device will come out of reset when Vdd rises above the brown-out voltage. The brown-out level can be set to 2.2V, 2.6V, OR 4.2V levels through BOR1:BOR0 bits in the FUSEX register.
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14.0 REGISTER STATES UPON DIFFERENT RESET CONDITIONS
The effect of different reset operations on a register depends on the register and the type of reset operation. Some registers are initialized to specific values, some are left unchanged, some are undefined, and some initialized to an unknown value.
A register that starts with an unknown value should be initialized by the software to a known value; you cannot simply test the initial state and rely on it starting in that state consistently. Table 14-1 lists the SX registers and shows the state of each register upon reset, with a different column for each type of reset.
Table 14-1. Register States Upon Different Resets Register W OPTION MODE RTCC (01h) PC (02h) STATUS (03h) Power-On Undefined FFh 1Fh Undefined FFh Bits 0-2: Undefined Bits 3-4: 11 Bits 5-7: 000 FSR (04h) Undefined Wakeup Unchanged FFh 1Fh Unchanged FFh Bits 0-2: Unchanged Bits 3-4: Unch. Bits 5-7: 000 Bits 0-6: Unchanged Bit 7: 1 RA through RE Direction RA through RE Data Other File Registers SRAM CMP_B Undefined Undefined Bits 0, 6-7: 1 Bits 1-5: Undefined WKPND_B WKED_B WKEN_B ST_B through ST_E LVL_A through LVL_E PLP_A through PLP_E Watchdog Counter Undefined FFh FFh FFh FFh FFh Undefined Unchanged Unchanged Bits 0, 6-7: 1 Bits 1-5: Undefined Unchanged FFh FFh FFh FFh FFh Unchanged 01 00 Undefined Undefined Bits 0, 6-7: 1 Bits 1-5: Undefined Undefined FFh FFh FFh FFh FFh Undefined 01 00 Unchanged Unchanged Bits 0, 6-7: 1 Bits 1-5: Undefined Unchanged FFh FFh FFh FFh FFh Unchanged 01 00 Unchanged Unchanged Bits 0, 6-7: 1 Bits 1-5: Undefined Unchanged FFh FFh FFh FFh FFh Unchanged 01 00 FFh FFh Bits 0-6: Undefined Bit 7: 1 FFh Brown-out Undefined FFh 1Fh Undefined FFh Bits 0-4: Undefined Bits 5-7: 000 Watchdog Timeout Unchanged FFh 1Fh Unchanged FFh Bits 0-2: Unchanged Bits 5-7: 000 Bits 0-6: Unchanged Bit 7: 1 FFh FFh 1Fh Unchanged FFh Bits 0-2: Unchanged Bits 5-7:000 Bits 0-6: Unchanged Bit 7: 1 FFh MCLR Unchanged
Bits 3-4: (Note 1) Bits 3-4: (Note 2)
Timers T1 and T2 Free- 01 Running Timer/Counter Timers T1 and T2 Con- 00 trol, Compare/Capture Registers NOTE: NOTE:
1. Watchdog reset during power down mode: 00 (bits TO, PD) Watchdog reset during Active mode: 01 (bits TO, PD) 2. External reset during power down mode: 10 (bits TO, PD) External reset during Active mode: Unchanged (bits TO, PD)
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SX52BD100
15.0 INSTRUCTION SET
As mentioned earlier, the SX family of devices uses a modified Harvard architecture with memory-mapped input/output. The device also has a RISC type architecture in that there are 43 single-word basic instructions. The instruction set contains byte-oriented file register, bitoriented file register, and literal/control instructions. Working register W is one of the CPU registers, which serves as a pseudo accumulator. It is a pseudo accumulator in a sense that it holds the second operand, receives the literal in the immediate type instructions, and also can be program-selected as the destination register. The bank of 31 file registers can also serve as the primary accumulators, but they represent the first operand and may be program-selected as the destination registers.
15.2
Instruction Execution
An instruction goes through a four-stage pipeline to be executed (Figure 15-1). The first instruction is fetched from the program memory on the first clock cycle. On the second clock cycle, the first instruction is decoded and the second instruction is fetched. On the third clock cycle, the first instruction is executed, the second instruction is decoded, and the third instruction is fetched. On the fourth clock cycle, the first instruction's results are written to its destination, the second instruction is executed, the third instruction is decoded, and the fourth instruction is fetched. Once the pipeline is full, instructions are executed at the rate of one per clock cycle. Instructions that directly affect the contents of the program counter (such as jumps and calls) require that the pipeline be cleared and subsequently refilled. Therefore, these instructions take more than one clock cycle. The instruction execution time is derived by dividing the oscillator frequency by one (bit 11 of the FUSE Word register must be initialized to 0).
15.1 Instruction Set Features
1. All single-word (12-bit) instructions for compact code efficiency. 2. All instructions are single cycle except the jump type instructions (JMP, CALL) and failed test instructions (DECSZ fr, INCSZ fr, SB bit, SNB bit), which are twocycle. 3. A set of file registers can be addressed directly or indirectly, and serve as accumulators to provide first operand; W register provides the second operand. 4. Many instructions include a destination bit which selects either the register file or the accumulator as the destination for the result. 5. Bit manipulation instructions (Set, Clear, Test and Skip if Set, Test and Skip if Clear). 6. STATUS Word register memory-mapped as a register file, allowing testing of status bits (carry, digit carry, zero, power down, and timeout). 7. Program Counter (PC) memory-mapped as register file allows W to be used as offset register for indirect addressing of program memory. 8. Indirect addressing data pointer FSR (file select register) memory-mapped as a register file. 9. IREAD instruction allows reading the instruction from the program memory addressed by W and upper four bits of MODE register. 10.Eight-level, 12-bit push/pop hardware stack for subroutine linkage using the Call and Return instructions. 11.Seven addressing mode provide great flexibility.
Fetch
Decode
Execute
Write
Clock Cycle 1
Clock Cycle 2
Clock Cycle 3
Clock Cycle 4
Figure 15-1. Pipeline and Clock Scheme
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15.3 Addressing Modes
The device support the following addressing modes: Data Direct Data Indirect Data Semidirect Immediate Program Direct Program Indirect Relative Both direct and indirect addressing modes are available. The INDF register, though physically not implemented, is used in conjunction with the indirect data pointer (FSR) to perform indirect addressing. An instruction using INDF as its operand field actually performs the operation on the register pointed by the contents of the FSR. Consequently, processing two multiple-byte operands requires alternate loading of the operand addresses into the FSR pointer as the multiple byte data fields are processed. Examples: Direct addressing:
mov mov W,#1 RA,W ;move "1" to RA
figures each port pin as a Hi-Z input or output. The second register (TTL/CMOS Register), selects the desired input level for the input. The third register (Pull-Up Register), enables a weak pull-up resistor on the pin configured as a input. To read or write these registers, you must first write an appropriate value into the MODE register to select the desired register set, and then use the "mov !rx,W" instruction to read or write the register. 15.6.1 Read-Modify-Write Considerations When two successive instructions are used on the same I/O port (except "mov Rx, W") with a very high clock rate, the "write" part of one instruction might not occur soon enough before the "read" part of the very next instruction, resulting in getting "old" data for the second instruction. To ensure predictable results, avoid using two successive read-modify-write instructions that access the same port data register if the clock rate is high or, insert a single NOP instruction between the successive read-modify-write instructions (if SYNC bit in the FUSE register is enabled, 2 NOP instructions are required). If bit 7 of the T2CNTB (PORTRD) is set, the port read opeartion operation reads data from the data register instead of port pins. In this case, the NOP instructions are not required. In the default device configuration, when a read is performed from a port bit position, the operation is actually reading the voltage level on the pin itself, not necessarily the bit value stored in the port data register. This is true whether the pin is configured to operate as an input or an output. Therefore, with the pin configured to operate as an input, the data register contents have no effect on the value that you read. With the pin configured to operate as an output, what is read generally matches what has been written to the register. PORTRD of the T2CNTB register determines how the device reads data from its I/O ports (Port A through Port E). Clear this bit to 0 to have the device read data from the port I/O pins directly. Set this bit to 1 to have the device read data from the port data registers. Under normal output mode conditions, it should not matter which method you use to read the port data. However, if a port pin is configured as an output and an external circuit forces the pin to the opposite value, the value read from the port will depend on the reading mode used. Note that this control bit is not related to multi-function timers T1 and T2.
Indirect Addressing:
mov mov mov W,#RA FSR,W INDF,#$01 ;FSR = address of RA ;move "1" to RA
Semidirect Addressing:
mov mov inc W,#$00 FSR,W $1F ;FSR = bank 0 address ;increment file ;register 0Fh
15.4 The Bank Instruction
Often it is desirable to set the bank select bits of the FSR register in one instruction cycle. The Bank instruction provides this capability. This instruction sets the upper 3 bits 4, 5 and 6 of the FSR to point to a specific RAM bank without affecting the lower 4 FSR bits, in preparation for using direct or semidirect addressing. Bit 7 of the FSR register is used to select the lower or upper block of banks. Example:
bank $E0 inc $1F ;Select Bank E in FSR ;increment file register ;EFh using semidirect addressing
15.7
Increment/Decrement
The current selected bank of 31 registers serves as a set of accumulators. The instruction set contains instructions to increment and decrement the register file. The device also includes both INCSZ fr (increment file register and skip if zero) and DECSZ fr (decrement file register and skip if zero) instructions.
15.5 Bit Manipulation
The instruction set contains instructions to set, reset, and test individual bits in data memory. The device is capable of bit addressing anywhere in data memory.
15.8
Loop Counting and Data Pointing Testing
15.6 Input/Output Operation
The device contains three registers associated with each I/O port. The first register (Data Direction Register), con(c) 2000 Scenix Semiconductor, Inc. All rights reserved.
The device has specific instructions to facilitate loop counting. The DECSZ fr (decrement file register and skip if zero) tests any one of the file registers and skips the next instruction (which can be a branch back to loop) if the result is zero.
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15.9 Branch and Loop Call Instructions
The device contains an 8-level hardware stack where the return address is stored with a subroutine call. Multiple stack levels allow subroutine nesting. The instruction set supports absolute address branching. 15.9.1 Jump Operation When a JMP instruction is executed, the lower nine bits of the program counter are loaded with the address of the specified label. The upper three bits of the program counter are loaded with the page select bits, PA2:PA0, contained in the STATUS register. Therefore, care must be exercised to ensure the page select bits are pointing to the correct page before the jump occurs.
STATUS<7:5> JMP LABEL (9 BITS) STATUS<7:5> PC<11:9> PC<8:0> PC<11:9> PC<8> PC<7:0> 0 CALL LABEL (8 BITS) STATUS<7:5> 0 CALL LABEL (8 BITS)
PC<11:9>
PC<8>
PC<7:0>
is executed. This can be done easily using SETB and CLRB instructions or writing a value to the STATUS register. The device also has the PAGE instruction, which automatically selects the page in a single-cycle execution.
PAGE N
15.9.2 Page Jump Operation When a JMP instruction is executed and the intended destination is on a different page, the page select bits must be initialized with appropriate values to point to the desired page before the jump occurs. This can be done easily with SETB and CLRB instructions or by writing a value to the STATUS register. The device also has the PAGE instruction, which automatically selects the page in a single-cycle execution.
PAGE N
15.10 Return Instructions
The device has several instructions for returning from subroutines and interrupt service routines. The return from subroutine instructions are RET (return without affecting W), RETP (same as RET but affects PA2:PA0), RETI (return from interrupt), RETIW (return and add W to RTCC), and RETW #literal (return and place literal in W). The literal serves as an immediate data value from memory. This instruction can be used for table lookup operations. To do table lookup, the table must contain a string of RETW #literal instructions. The first instruction just in front of the table calculates the offset into the table. The table can be used as a result of a CALL.
STATUS<7:5>
JMP LABEL (9 BITS)
PC<11:9>
PC<8:0>
Note:"N" must be 0, 1, 2, or 3. 15.9.3 Call Operation The following happens when a CALL instruction is executed: * The current value of the program counter is incremented and pushed onto the top of the stack. * The lower eight bits of the label address are copied into the lower eight bits of the program counter. * The ninth bit of the Program Counter is cleared to zero. * The page select bits (in STATUS register) are copied into the upper three bits of the 12-bit program counter. This means that the call destination must start in the lower half of any page. For example, 00h-0FFh, 200h2FFh, 400h-4FFh, etc. 15.9.4 Page Call Operation When a subroutine that resides on a different page is called, the page select bits must contain the proper values to point to the desired page before the call instruction
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15.11 Subroutine Operation
15.11.1 Push Operation When a subroutine is called, the return address is pushed onto the subroutine stack. Specifically, each address in the stack is moved to the next lower level in order to make room for the new address to be stored. Stack 1 receives the contents of the program counter. Stack 8 is overwritten with what was in Stack 7. The contents of stack 8 are lost.
15.11.2 Pop Operation When a return instruction is executed the subroutine stack is popped. Specifically, the contents of Stack 1 are copied into the program counter and the contents of each stack level are moved to the next higher level. For example, Stack 1 receives the contents of Stack 2, etc., until Stack 7 is overwritten with the contents of Stack 8. Stack 8 is left unchanged, so the contents of Stack 8 are duplicated in Stack 7.
PC<11:0> PC<11:0> STACK 1 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 STACK 8 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 STACK 8
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15.12 Comparison and Conditional Branch Instructions
The instruction set includes instructions such as DECSZ fr (decrement file register and skip if zero), INCSZ fr (increment file register and skip if zero), SNB bit (bit test file register and skip if bit clear), and SB bit (bit test file register and skip if bit set). These instructions will cause the next instruction to be skipped if the tested condition is true. If a skip instruction is immediately followed by a PAGE or BANK instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles. This is useful for conditional branching to another page where a PAGE instruction precedes a JMP. If several PAGE and BANK instructions immediately follow a skip instruction then they are all skipped plus the next instruction and a cycle is consumed for each.
15.16 Key to Abbreviations and Symbols
Symbol W fr PC Working register File register (memory-mapped register in the range of 00h to FFh) Lower eight bits of program counter (file register 02h) File Select Register (file register 04h) Carry bit in STATUS register (bit 0) Digit Carry bit in STATUS register (bit 1) Zero bit in STATUS register (bit 2 Power Down bit in STATUS register (bit 3) Watchdog Timeout bit in STATUS register (bit 4) Description
STATUS STATUS register (file register 03h) FSR C DC Z PD TO
15.13 Logical Instruction
The instruction set contain a full complement of the logical instructions (AND, OR, Exclusive OR), with the W register and a selected memory location (using either direct or indirect addressing) serving as the two operands.
PA2:PA0 Page select bits in STATUS register (bits 7:5) OPTION OPTION register (not memory-mapped) WDT MODE rx ! f k n b . # lit addr8 addr9 addr12 / | ^ & <> << >> -++ Watchdog Timer register (not memorymapped) MODE register (not memory-mapped) Port control register pointer (RA, RB, RC, RD, RE) Non-memory-mapped register designator File register address bit in opcode Constant value bit in opcode Numerical value bit in opcode Bit position selector bit in opcode File register / bit selector separator in assembly language instruction Immediate literal designator in assembly language instruction Literal value in assembly language instruction 8-bit address in assembly language instruction 9-bit address in assembly language instruction 12-bit address in assembly language instruction Logical 1's complement Logical OR Logical exclusive OR Logical AND Swap high and low nibbles (4-bit segments) Rotate left through carry flag Rotate right through carry flag Decrement file register Increment file register
15.14 Shift and Rotate Instructions
The instruction set includes instructions for left or right rotate-through-carry.
15.15 Complement and SWAP
The device can perform one's complement operation on the file register (fr) and W register. The MOV W,<>fr instruction performs nibble-swap on the fr and puts the value into the W register.
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16.0 INSTRUCTION SET SUMMARY TABLE
Table 16-1 lists all of the instructions, organized by category. For each instruction, the table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycles required for execution, the binary opcode, and the status flags affected by the instruction. The "Cycles" column typically shows a value of 1, which means that the overall throughput for the instruction is one per clock cycle. In some cases, the exact number of Table 16-1. The SX Instruction Set Mnemonic, Operands Logical Operations AND fr, W AND W, fr AND W,#lit NOT fr OR fr,W OR W,fr OR W,#lit XOR fr,W XOR W,fr XOR W,#lit AND of fr and W into fr (fr = fr & W) AND of W and fr into W (W = W & fr) AND of W and Literal into W (W = W & lit) Complement of fr into fr (fr = fr ^ FFh) OR of fr and W into fr (fr = fr | W) OR of W and fr into fr (W = W | fr) OR of W and Literal into W (W = W | lit) XOR of fr and W into fr (fr = fr ^ W) XOR of W and fr into W (W = W ^ fr) XOR of W and Literal into W (W = W ^ lit) 1 1 1 1 1 1 1 1 1 1 0001 011f ffff 0001 010f ffff 1110 kkkk kkkk 0010 011f ffff 0001 001f ffff 0001 000f ffff 1101 kkkk kkkk 0001 101f ffff 0001 100f ffff 1111 kkkk kkkk Z Z Z Z Z Z Z Z Z Z Description Cycles Opcode Flags Affected cycles depends on the outcome of the instruction (such as the test-and-skip instructions). In those cases, all possible numbers of cycles are shown in the table. The instruction execution time is derived by dividing the oscillator frequency by one (bit 11 of the FUSE Word register must be initialized to 0).
Arithmetic and Shift Operations ADD fr,W ADD W,fr CLR fr CLR W CLR !WDT DEC fr DECSZ fr INC fr INCSZ fr RL fr RR fr SUB fr,W Add W to fr (fr = fr + W); carry flag is added if CF bit in FUSEX register is cleared to 0 Add fr to W (W = W + fr); carry flag is added if CF bit in FUSEX register is cleared to 0 Clear fr (fr = 0) Clear W (W = 0) Clear Watchdog Timer (TO = 1, PD = 1, clears prescaler if assigned) Decrement fr (fr = fr - 1) 1 1 1 1 1 1 0001 111f ffff 0001 110f ffff 0000 011f ffff 0000 0100 0000 0000 0000 0100 0000 111f ffff C, DC, Z C, DC, Z Z Z TO, PD Z none Z none C C C, DC, Z
Decrement fr and Skip if Zero (fr = fr - 1 and skip 1 or 0010 111f ffff next instruction if result is zero) 2 (skip) Increment fr (fr = fr + 1) 1 0010 101f ffff
Increment fr and Skip if Zero (fr = fr + 1 and skip 1 or 0011 111f ffff next instruction if result is zero) 2 (skip) Rotate fr Left through Carry (fr = << fr) Rotate fr Right through Carry (fr = >> fr) Subtract W from fr (fr = fr - W); complement of the carry flag is subtracted if CF bit in FUSEX register is cleared to 0 Swap High/Low Nibbles of fr (fr = <> fr) 1 1 1 0011 011f ffff 0011 001f ffff 0000 101f ffff
SWAP fr
1
0011 101f ffff
none
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SX52BD100
Table 16-1. The SX Instruction Set (Continued) Mnemonic, Operands Bitwise Operations CLRB fr.bit SB fr.bit SETB fr.bit SNB fr.bit Clear Bit in fr (fr.bit = 0) 1 0100 bbbf ffff none none none none Description Cycles Opcode Flags Affected
Test Bit in fr and Skip if Set (test fr.bit and skip 1 or 0111 bbbf ffff next instruction if bit is 1) 2 (skip) Set Bit in fr (fr.bit = 1) 1 0101 bbbf ffff
Test Bit in fr and Skip if Clear (test fr.bit and skip 1 or 0110 bbbf ffff next instruction if bit is 0) 2 (skip)
Data Movement Instructions MOV fr,W MOV W,fr MOV W,fr-W Move W to fr (fr = W) Move fr to W (W = fr) Move (fr-W) to W (W = fr - W); complement of carry flag is subtracted if CF bit in FUSEX register is cleared to 0 Move Literal to W (W = lit) Move Complement of fr to W (W = fr ^ FFh) Move (fr-1) to W (W = fr - 1) Move (fr+1) to W (W = fr + 1) Rotate fr Left through Carry and Move to W (W = << fr) Rotate fr Right through Carry and Move to W (W = >> fr) Swap High/Low Nibbles of fr and move to W (W = <> fr) Move MODE Register to W (W = MODE), high nibble of W cleared 1 1 1 0000 001f ffff 0010 000f ffff 0000 100f ffff none Z C, DC, Z
MOV W,#lit MOV W,/fr MOV W,--fr MOV W,++fr MOV W,<>fr MOV W,<>fr MOV W,M MOVSZ W,--fr MOVSZ W,++fr MOV M,W MOV M,#lit MOV !rx,W
1 1 1 1 1 1 1 1
1100 kkkk kkkk 0010 010f ffff 0000 110f ffff 0010 100f ffff 0011 010f ffff 0011 000f ffff 0011 100f ffff 0000 0100 0010
none Z Z Z C C none none none none none none none
Move (fr-1) to W and Skip if Zero (W = fr -1 and 1 0010 110f ffff skip next instruction if result is zero) 2 (skip) Move (fr+1) to W and Skip if Zero (W = fr + 1 and 1 0011 110f ffff skip next instruction if result is zero) 2 (skip) Move W to MODE Register (MODE = W) Move Literal to MODE Register (MODE = lit) Move Data Between W and Control Register: rx = W (move W to rx) or W = rx (move rx to W) or rx <=> W (exchange W and rx) 1 1 1 0000 0100 0011 0000 0101 kkkk 0000 0000 ffff
MOV !OPTION, W Move W to OPTION Register (OPTION = W) TEST fr Test fr for Zero (fr = fr to set or clear Z flag)
1 1
0000 0000 0010 0010 001f ffff
none Z
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SX52BD100
Table 16-1. The SX Instruction Set (Continued) Mnemonic, Operands Program Control Instructions CALL addr8 Call Subroutine: top-of-stack = program counter + 1 PC(7:0) = addr8 program counter (8) = 0 program counter (11:9) = PA2:PA0 Jump to Address: PC(7:0) = addr9(7:0) program counter (8) = addr9(8) program counter (11:9) = PA2:PA0 No Operation Return from Subroutine (program counter = top-of-stack) Return from Subroutine Across Page Boundary (PA2:PA0 = top-of-stack (11:9) and program counter = top-of-stack) Return from Interrupt (restore W, STATUS, FSR, MODE and program counter from shadow registers) Return from Interrupt and add W to RTCC (restore W, STATUS, FSR, MODE and program counter from shadow registers; and add W to the RTCC register) Return from Subroutine with Literal in W (W = lit and program counter = top-of-stack) 3 1001 kkkk kkkk none Description Cycles Opcode Flags Affected
JMP addr9
3
101k kkkk kkkk
none
NOP RET RETP
1 3 3
0000 0000 0000 0000 0000 1100 0000 0000 1101
none none PA1, PA0
RETI
3
0000 0000 1110
all STATUS except TO, PD bits all STATUS except TO, PD bits
RETIW
3
0000 0000 1111
RETW lit
3
1000 kkkk kkkk
none
System Control Instructions BANK addr12 IREAD PAGE addr12 SLEEP Load Bank Number into FSR(6:4) FSR(6:4) = addr12(10:8) Read Word from Instruction Memory MODE:W = data at address (MODE:W) Load Page Number into STATUS(7:5) STATUS(7:5) = addr12(11:9) Power Down Mode WDT = 00h, TO = 1, stop oscillator (PD = 0, clear prescaler if assigned) 1 4 1 1 0000 0001 1nnn 0000 0100 0001 0000 0001 0nnn 0000 0000 0011 none none PA2, PA1, PA0 TO, PD
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SX52BD100
16.1 Equivalent Assembler Mnemonics
Some assemblers support additional instruction mnemonics that are special cases of existing instructions or alternative mnemonics for standard ones. For example, an assembler might support the mnemonic "CLC" (clear carry), which is interpreted the same as the instruction
"clrb $03.0" (clear bit 0 in the STATUS register). Some of the commonly supported equivalent assembler mnemonics are described in Table 16-2.
Table 16-2. Equivalent Assembler Mnemonics Syntax CLC CLZ JMP W JMP PC+W MODE imm4 NOT W SC SKIP Description Clear Carry Flag Clear Zero Flag Jump Indirect W Jump Indirect W Relative Move Immediate to MODE Register Complement W Skip if Carry Flag Set Skip Next Instruction Equivalent CLRB $03.0 CLRB $03.2 MOV $02,W ADD $02,W MOV M,#lit XOR W,#$FF SB $03.0 SNB $02.0 or SB $02.0 Cycles 1 1 3 3 1 1 1 or 2 (note 1) 2 (note 2)
Note 1: The SC instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true. Note 2: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit of the program counter, choosing SNB or SB so that the tested condition is always true.
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SX52BD100
17.0 ELECTRICAL CHARACTERISTICS 17.1 Absolute Maximum Ratings (beyond which permanent damage may occur)
Ambient temperature under bias Storage temperature Voltage on Vdd with respect to Vss Voltage on OSC1 with respect to Vss Voltage on MCLR with respect to Vss Voltage on all other pins with respect to V ss Total power dissipation 0C to +70C -65C to +150C 0 V to +7.0 V 0 V to +13.5 V 0 V to +13.5 V - 0.6 V to (Vdd + 0.6 V) V 1 W at 70C 1.5 W at 25C Max. current out of Vss pins 180 mA at 70C 300 mA at 25C Max. current into Vdd pins 180 mA at 70C 300 mA at 25C Max. DC current into an input pin (with internal protection diode forward biased) Max. allowable sink current per I/O pin Max. allowable source current per I/O pin Max. allowable sink current per group of I/O pins between Vdd pins Max. allowable source current per group of I/O pins between Vdd pins Latchup JA, 52-pin Package Number of EEPROM Write Cycles ESD Human Body Model - all pins ESD Machine Model - all pins +500 A 45 mA 45 mA 50 mA 50 mA 200 mA 82C/W 10,000 2000V 200V
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SX52BD100
17.2 DC Characteristics
Operating Temperature 0C <= Ta <= +70C (Commercial) Symbol Vdd SVdd Idd Ipd Vih, Vil Parameter Supply Voltage (Note 1) Vdd rise rate to ensure PowerOn Reset Supply Current, active Supply Current, power down Input Levels MCLR, OSC1, RTCC Logic High Logic Low All Other Inputs CMOS Logic High Logic Low TTL Logic High Logic Low Iil Ipup Voh Input Leakage Current Weak Pullup Current Output High Voltage OSC2, Ports B, C, D, E Port A Vol Output Low Voltage OSC2, All Ports Note 1: Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset Circuitry. Ioh = 20mA, Vdd = 4.75V Ioh = 30mA, Vdd = 4.75V Iol = 30mA, Vdd = 4.75V Vdd-0.7 Vdd-0.7 0.6 V V V Vin = Vdd or Vss Vdd = 5.5V, Vin = 0V 2.0 Vss -3.0 Vdd 0.8 3.0 400 V V A A 0.7Vdd Vss Vdd 0.3Vdd V V 0.8Vdd Vss Vdd 0.2Vdd V V Vdd = 5.0V, Fosc = 100 MHz Vdd = 5.0V, WDT disabled Conditions Min 4.75 0.05 Typ 5 - 180 Max 5.25 - 100 Units V V/ms mA A
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SX52BD100
17.3 AC Characteristics
Operating Temperature 0C <= Ta <= +70C (Commercial) Symbol Fosc Parameter External CLKIN Frequency Min DC Typ Max 4.0 10 24 100 32 1.0 Oscillator Frequency DC 0.032 1.0 1.0 DC 0.032 Tosc External CLKIN Period 250 100 41.7 20 31.25 1.0 Oscillator Period 250 0.1 41.7 20 31.25 1.0 TosL, TosH Clock in (OSC1) Low or High Time 50 8.0 2.0 TosR, TosF Clock in (OSC1) Rise or Fall Time 25 25 50 Note:Data in the Typical ("TYP") column is at 5V, 25C unless otherwise stated. Internal RC Oscillator AC specs are still being characterized. Internal RC oscillator frequency is 4MHz 8% (typical). 31.25 1000.0 1000.0 31.25 ns ns s ns ns s 4.0 10.0 24.0 100 32 1.0 Units MHz MHz MHz MHz KHz MHz MHz MHz MHz MHz KHz MHz ns ns ns ns s s ns s ns ns s Conditions RC XT1 XT2 HS1/HS2/HS3 LP1 LP2 RC XT1 XT2 HS1/HS2/HS3 LP1 LP2 RC XT1 XT2 HS1/HS2/HS3 LP1 LP2 RC XT1 XT2 HS1/HS2/HS3 LP1 LP2 XT1/XT2 HS1/HS2/HS3 LP1/LP2 XT1/XT2 HS1/HS2/HS3 LP1/LP2
17.4 Comparator DC and AC Specifications
Parameter Input Offset Voltage Input Common Mode Voltage Range Voltage Gain Response Time Voverdrive = 25 mV Conditions 0V < Vin < Vdd 0 300k 250 Min Typ +/- 10 Max +/- 25 Vdd Units mV V V/V ns
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SX52BD100
18.0 PACKAGE DIMENSIONS [DIMENSIONS ARE IN INCHES/(MILLIMETERS)]
SX52BD/PQ
0.0806 - 0.0889 (2.05 - 2.25) 0.511 - 0.527 (13.0 - 13.4) 0.391 - 0.395 (9.95 - 10.05) 0.306 (7.80) 0.0365 (0.93) 0.079 (2.0)
bottom of body
0.012 (0.3)
0.0255 (0.65) 7
0.0039-0.008 (0.1 - 0.2)
0.306 (7.80) 0.391 - 0.395 (9.95 - 10.05)
0.511 - 0.527 (13.0 - 13.4)
5 5 0.0275 - 0.0354 (0.7 - 0.9)
0.059 - 0.067 (1.5 - 1.7)
(c) 2000 Scenix Semiconductor, Inc. All rights reserved.
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SX52BD100
Lit #: SXL-DS04-01
Sales and Tech Support Contact Information
For the latest contact and support information on SX devices, please visit the Scenix Semiconductor website at www.scenix.com. The site contains technical literature, local sales contacts, tech support and many other features.
1330 Charleston Road Mountain View, CA 94043 Tel.: (650) 210-1500 Fax: (650) 210-8715 E-Mail: sales@scenix.com Web Site: www.scenix.com
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